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https://github.com/brain-hackers/u-boot-brain
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8ed74341ba
For the kmsupx5 a new header file was introduced km8321-common.h. Now the common stuff from tuxa1, tuda1 and suvd3 was removed and the new header file included. The defines CONFIG_SYS_PIGGY_BASE and CONFIG_SYS_PIGGY_SIZE are confusing. Because they actually describe the KMBEC FPGA values. The KMBEC FPGA can be PRIO on kmeter1 or upio on mgcoge. Therefore all the defines were renamed. remove unneeded variable CONFIG_KM_DEF_NETDEV, as it is already declared in keymile-common.h Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> cc: Kim Phillips <kim.phillips@freescale.com> cc: Wolfgang Denk <wd@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com>
105 lines
3.0 KiB
C
105 lines
3.0 KiB
C
/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*
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* Copyright (C) 2007 Logic Product Development, Inc.
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* Peter Barada <peterb@logicpd.com>
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* (C) Copyright 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_SUVD3 /* SUVD3 board specific */
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#define CONFIG_HOSTNAME suvd3
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#define CONFIG_KM_BOARD_NAME "suvd3"
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#define CONFIG_SYS_TEXT_BASE 0xF0000000
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/* include common defines/options for all 8321 Keymile boards */
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#include "km8321-common.h"
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#define CONFIG_SYS_APP1_BASE 0xA0000000
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#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
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#define CONFIG_SYS_APP2_BASE 0xB0000000
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#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
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/* EEprom support */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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/*
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* Init Local Bus Memory Controller:
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*
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* Bank Bus Machine PortSz Size Device
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* ---- --- ------- ------ ----- ------
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* 2 Local UPMA 16 bit 256MB APP1
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* 3 Local GPCM 16 bit 256MB APP2
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*
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*/
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/*
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* APP1 on the local bus CS2
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*/
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#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
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#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
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#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
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BR_PS_16 | \
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BR_MS_UPMA | \
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BR_V)
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#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
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#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
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BR_PS_16 | \
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BR_V)
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#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
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OR_GPCM_CSNT | \
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OR_GPCM_ACS_DIV4 | \
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OR_GPCM_SCY_3 | \
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OR_GPCM_TRLX)
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#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
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0x0000c000 | \
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MxMR_WLFx_2X)
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#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
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#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
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/*
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* MMU Setup
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*/
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/* APP1: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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#endif /* __CONFIG_H */
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