252 lines
7.7 KiB
C
252 lines
7.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* TI K3 AM65x NAVSS Ring accelerator Manager (RA) subsystem driver
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*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
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*/
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#ifndef __SOC_TI_K3_NAVSS_RINGACC_API_H_
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#define __SOC_TI_K3_NAVSS_RINGACC_API_H_
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#include <dm/ofnode.h>
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#include <linux/bitops.h>
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/**
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* enum k3_nav_ring_mode - &struct k3_nav_ring_cfg mode
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*
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* RA ring operational modes
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*
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* @K3_NAV_RINGACC_RING_MODE_RING: Exposed Ring mode for SW direct access
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* @K3_NAV_RINGACC_RING_MODE_MESSAGE: Messaging mode. Messaging mode requires
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* that all accesses to the queue must go through this IP so that all
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* accesses to the memory are controlled and ordered. This IP then
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* controls the entire state of the queue, and SW has no directly control,
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* such as through doorbells and cannot access the storage memory directly.
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* This is particularly useful when more than one SW or HW entity can be
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* the producer and/or consumer at the same time
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* @K3_NAV_RINGACC_RING_MODE_CREDENTIALS: Credentials mode is message mode plus
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* stores credentials with each message, requiring the element size to be
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* doubled to fit the credentials. Any exposed memory should be protected
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* by a firewall from unwanted access
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* @K3_NAV_RINGACC_RING_MODE_QM: Queue manager mode. This takes the credentials
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* mode and adds packet length per element, along with additional read only
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* fields for element count and accumulated queue length. The QM mode only
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* operates with an 8 byte element size (any other element size is
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* illegal), and like in credentials mode each operation uses 2 element
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* slots to store the credentials and length fields
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*/
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enum k3_nav_ring_mode {
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K3_NAV_RINGACC_RING_MODE_RING = 0,
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K3_NAV_RINGACC_RING_MODE_MESSAGE,
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K3_NAV_RINGACC_RING_MODE_CREDENTIALS,
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K3_NAV_RINGACC_RING_MODE_QM,
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k3_NAV_RINGACC_RING_MODE_INVALID
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};
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/**
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* enum k3_nav_ring_size - &struct k3_nav_ring_cfg elm_size
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*
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* RA ring element's sizes in bytes.
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*/
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enum k3_nav_ring_size {
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K3_NAV_RINGACC_RING_ELSIZE_4 = 0,
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K3_NAV_RINGACC_RING_ELSIZE_8,
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K3_NAV_RINGACC_RING_ELSIZE_16,
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K3_NAV_RINGACC_RING_ELSIZE_32,
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K3_NAV_RINGACC_RING_ELSIZE_64,
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K3_NAV_RINGACC_RING_ELSIZE_128,
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K3_NAV_RINGACC_RING_ELSIZE_256,
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K3_NAV_RINGACC_RING_ELSIZE_INVALID
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};
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struct k3_nav_ringacc;
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struct k3_nav_ring;
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/**
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* enum k3_nav_ring_cfg - RA ring configuration structure
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*
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* @size: Ring size, number of elements
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* @elm_size: Ring element size
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* @mode: Ring operational mode
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* @flags: Ring configuration flags. Possible values:
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* @K3_NAV_RINGACC_RING_SHARED: when set allows to request the same ring
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* few times. It's usable when the same ring is used as Free Host PD ring
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* for different flows, for example.
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* Note: Locking should be done by consumer if required
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*/
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struct k3_nav_ring_cfg {
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u32 size;
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enum k3_nav_ring_size elm_size;
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enum k3_nav_ring_mode mode;
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#define K3_NAV_RINGACC_RING_SHARED BIT(1)
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u32 flags;
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};
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#define K3_NAV_RINGACC_RING_ID_ANY (-1)
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/**
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* k3_nav_ringacc_request_ring - request ring from ringacc
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* @ringacc: pointer on ringacc
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* @id: ring id or K3_NAV_RINGACC_RING_ID_ANY for any general purpose ring
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*
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* Returns pointer on the Ring - struct k3_nav_ring
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* or NULL in case of failure.
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*/
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struct k3_nav_ring *k3_nav_ringacc_request_ring(struct k3_nav_ringacc *ringacc,
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int id);
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int k3_nav_ringacc_request_rings_pair(struct k3_nav_ringacc *ringacc,
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int fwd_id, int compl_id,
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struct k3_nav_ring **fwd_ring,
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struct k3_nav_ring **compl_ring);
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/**
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* k3_nav_ringacc_get_dev - get pointer on RA device
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* @ringacc: pointer on RA
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*
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* Returns device pointer
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*/
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struct udevice *k3_nav_ringacc_get_dev(struct k3_nav_ringacc *ringacc);
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/**
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* k3_nav_ringacc_ring_reset - ring reset
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* @ring: pointer on Ring
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*
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* Resets ring internal state ((hw)occ, (hw)idx).
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* TODO_GS: ? Ring can be reused without reconfiguration
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*/
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void k3_nav_ringacc_ring_reset(struct k3_nav_ring *ring);
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/**
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* k3_nav_ringacc_ring_reset - ring reset for DMA rings
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* @ring: pointer on Ring
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*
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* Resets ring internal state ((hw)occ, (hw)idx). Should be used for rings
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* which are read by K3 UDMA, like TX or Free Host PD rings.
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*/
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void k3_nav_ringacc_ring_reset_dma(struct k3_nav_ring *ring, u32 occ);
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/**
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* k3_nav_ringacc_ring_free - ring free
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* @ring: pointer on Ring
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*
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* Resets ring and free all alocated resources.
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*/
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int k3_nav_ringacc_ring_free(struct k3_nav_ring *ring);
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/**
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* k3_nav_ringacc_get_ring_id - Get the Ring ID
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* @ring: pointer on ring
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*
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* Returns the Ring ID
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*/
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u32 k3_nav_ringacc_get_ring_id(struct k3_nav_ring *ring);
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/**
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* k3_nav_ringacc_ring_cfg - ring configure
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* @ring: pointer on ring
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* @cfg: Ring configuration parameters (see &struct k3_nav_ring_cfg)
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*
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* Configures ring, including ring memory allocation.
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* Returns 0 on success, errno otherwise.
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*/
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int k3_nav_ringacc_ring_cfg(struct k3_nav_ring *ring,
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struct k3_nav_ring_cfg *cfg);
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/**
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* k3_nav_ringacc_ring_get_size - get ring size
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* @ring: pointer on ring
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*
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* Returns ring size in number of elements.
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*/
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u32 k3_nav_ringacc_ring_get_size(struct k3_nav_ring *ring);
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/**
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* k3_nav_ringacc_ring_get_free - get free elements
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* @ring: pointer on ring
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*
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* Returns number of free elements in the ring.
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*/
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u32 k3_nav_ringacc_ring_get_free(struct k3_nav_ring *ring);
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/**
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* k3_nav_ringacc_ring_get_occ - get ring occupancy
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* @ring: pointer on ring
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*
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* Returns total number of valid entries on the ring
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*/
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u32 k3_nav_ringacc_ring_get_occ(struct k3_nav_ring *ring);
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/**
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* k3_nav_ringacc_ring_is_full - checks if ring is full
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* @ring: pointer on ring
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*
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* Returns true if the ring is full
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*/
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u32 k3_nav_ringacc_ring_is_full(struct k3_nav_ring *ring);
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/**
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* k3_nav_ringacc_ring_push - push element to the ring tail
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* @ring: pointer on ring
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* @elem: pointer on ring element buffer
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*
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* Push one ring element to the ring tail. Size of the ring element is
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* determined by ring configuration &struct k3_nav_ring_cfg elm_size.
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*
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* Returns 0 on success, errno otherwise.
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*/
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int k3_nav_ringacc_ring_push(struct k3_nav_ring *ring, void *elem);
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/**
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* k3_nav_ringacc_ring_pop - pop element from the ring head
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* @ring: pointer on ring
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* @elem: pointer on ring element buffer
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*
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* Push one ring element from the ring head. Size of the ring element is
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* determined by ring configuration &struct k3_nav_ring_cfg elm_size..
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*
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* Returns 0 on success, errno otherwise.
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*/
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int k3_nav_ringacc_ring_pop(struct k3_nav_ring *ring, void *elem);
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/**
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* k3_nav_ringacc_ring_push_head - push element to the ring head
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* @ring: pointer on ring
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* @elem: pointer on ring element buffer
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*
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* Push one ring element to the ring head. Size of the ring element is
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* determined by ring configuration &struct k3_nav_ring_cfg elm_size.
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*
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* Returns 0 on success, errno otherwise.
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* Not Supported by ring modes: K3_NAV_RINGACC_RING_MODE_RING
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*/
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int k3_nav_ringacc_ring_push_head(struct k3_nav_ring *ring, void *elem);
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/**
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* k3_nav_ringacc_ring_pop_tail - pop element from the ring tail
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* @ring: pointer on ring
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* @elem: pointer on ring element buffer
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*
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* Push one ring element from the ring tail. Size of the ring element is
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* determined by ring configuration &struct k3_nav_ring_cfg elm_size.
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*
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* Returns 0 on success, errno otherwise.
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* Not Supported by ring modes: K3_NAV_RINGACC_RING_MODE_RING
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*/
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int k3_nav_ringacc_ring_pop_tail(struct k3_nav_ring *ring, void *elem);
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/* DMA ring support */
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struct ti_sci_handle;
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/**
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* struct struct k3_ringacc_init_data - Initialization data for DMA rings
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*/
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struct k3_ringacc_init_data {
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const struct ti_sci_handle *tisci;
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u32 tisci_dev_id;
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u32 num_rings;
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};
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struct k3_nav_ringacc *k3_ringacc_dmarings_init(struct udevice *dev,
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struct k3_ringacc_init_data *data);
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#endif /* __SOC_TI_K3_NAVSS_RINGACC_API_H_ */
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