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https://github.com/brain-hackers/u-boot-brain
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e9ccb2f526
Add core architecture code to support the px30 soc. This includes a separate tpl board file due to very limited sram size as well as a non-dm sdram driver, as this also has to fit into the tiny sram. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
42 lines
735 B
Plaintext
42 lines
735 B
Plaintext
if ROCKCHIP_PX30
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config TARGET_EVB_PX30
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bool "EVB_PX30"
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config ROCKCHIP_BOOT_MODE_REG
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default 0xff010200
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config SYS_SOC
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default "px30"
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config SYS_MALLOC_F_LEN
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default 0x400
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config SPL_SERIAL_SUPPORT
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default y
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config TPL_LDSCRIPT
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default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
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config TPL_TEXT_BASE
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default 0xff0e1000
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config TPL_MAX_SIZE
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default 10240
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config TPL_STACK
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default 0xff0e4fff
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config DEBUG_UART2_CHANNEL
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int "Mux channel to use for debug UART2"
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depends on DEBUG_UART_BOARD_INIT
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default 0
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help
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UART2 can use two different set of pins to route the output.
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For using the UART for early debugging the route to use needs
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to be declared (0 or 1).
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source "board/rockchip/evb_px30/Kconfig"
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endif
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