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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
711 lines
18 KiB
C
711 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Jagan Teki <jteki@openedev.com>
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* Christophe Ricard <christophe.ricard@gmail.com>
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*
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* Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
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*
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* Driver for McSPI controller on OMAP3. Based on davinci_spi.c
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* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Copyright (C) 2007 Atmel Corporation
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*
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* Parts taken from linux/drivers/spi/omap2_mcspi.c
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* Copyright (C) 2005, 2006 Nokia Corporation
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*
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* Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <spi.h>
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#include <malloc.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
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#define OMAP3_MCSPI1_BASE 0x48030100
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#define OMAP3_MCSPI2_BASE 0x481A0100
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#else
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#define OMAP3_MCSPI1_BASE 0x48098000
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#define OMAP3_MCSPI2_BASE 0x4809A000
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#define OMAP3_MCSPI3_BASE 0x480B8000
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#define OMAP3_MCSPI4_BASE 0x480BA000
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#endif
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#define OMAP4_MCSPI_REG_OFFSET 0x100
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struct omap2_mcspi_platform_config {
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unsigned int regs_offset;
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};
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/* per-register bitmasks */
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#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
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#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
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#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
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#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
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#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
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#define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0)
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#define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
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#define OMAP3_MCSPI_MODULCTRL_STEST BIT(3)
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#define OMAP3_MCSPI_CHCONF_PHA BIT(0)
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#define OMAP3_MCSPI_CHCONF_POL BIT(1)
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#define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2)
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#define OMAP3_MCSPI_CHCONF_EPOL BIT(6)
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#define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7)
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#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
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#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
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#define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12)
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#define OMAP3_MCSPI_CHCONF_DMAW BIT(14)
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#define OMAP3_MCSPI_CHCONF_DMAR BIT(15)
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#define OMAP3_MCSPI_CHCONF_DPE0 BIT(16)
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#define OMAP3_MCSPI_CHCONF_DPE1 BIT(17)
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#define OMAP3_MCSPI_CHCONF_IS BIT(18)
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#define OMAP3_MCSPI_CHCONF_TURBO BIT(19)
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#define OMAP3_MCSPI_CHCONF_FORCE BIT(20)
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#define OMAP3_MCSPI_CHSTAT_RXS BIT(0)
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#define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
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#define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
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#define OMAP3_MCSPI_CHCTRL_EN BIT(0)
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#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
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#define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0)
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#define MCSPI_PINDIR_D0_IN_D1_OUT 0
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#define MCSPI_PINDIR_D0_OUT_D1_IN 1
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#define OMAP3_MCSPI_MAX_FREQ 48000000
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#define SPI_WAIT_TIMEOUT 10
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/* OMAP3 McSPI registers */
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struct mcspi_channel {
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unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */
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unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */
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unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */
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unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */
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unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */
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};
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struct mcspi {
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unsigned char res1[0x10];
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unsigned int sysconfig; /* 0x10 */
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unsigned int sysstatus; /* 0x14 */
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unsigned int irqstatus; /* 0x18 */
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unsigned int irqenable; /* 0x1C */
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unsigned int wakeupenable; /* 0x20 */
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unsigned int syst; /* 0x24 */
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unsigned int modulctrl; /* 0x28 */
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struct mcspi_channel channel[4];
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/* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
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/* channel1: 0x40 - 0x50, bus 0 & 1 */
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/* channel2: 0x54 - 0x64, bus 0 & 1 */
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/* channel3: 0x68 - 0x78, bus 0 */
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};
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struct omap3_spi_priv {
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#ifndef CONFIG_DM_SPI
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struct spi_slave slave;
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#endif
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struct mcspi *regs;
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unsigned int cs;
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unsigned int freq;
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unsigned int mode;
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unsigned int wordlen;
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unsigned int pin_dir:1;
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};
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static void omap3_spi_write_chconf(struct omap3_spi_priv *priv, int val)
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{
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writel(val, &priv->regs->channel[priv->cs].chconf);
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/* Flash post writes to make immediate effect */
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readl(&priv->regs->channel[priv->cs].chconf);
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}
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static void omap3_spi_set_enable(struct omap3_spi_priv *priv, int enable)
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{
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writel(enable, &priv->regs->channel[priv->cs].chctrl);
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/* Flash post writes to make immediate effect */
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readl(&priv->regs->channel[priv->cs].chctrl);
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}
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static int omap3_spi_write(struct omap3_spi_priv *priv, unsigned int len,
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const void *txp, unsigned long flags)
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{
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ulong start;
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int i, chconf;
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chconf = readl(&priv->regs->channel[priv->cs].chconf);
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/* Enable the channel */
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omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
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chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
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chconf |= (priv->wordlen - 1) << 7;
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chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY;
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chconf |= OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(priv, chconf);
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for (i = 0; i < len; i++) {
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/* wait till TX register is empty (TXS == 1) */
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start = get_timer(0);
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while (!(readl(&priv->regs->channel[priv->cs].chstat) &
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OMAP3_MCSPI_CHSTAT_TXS)) {
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if (get_timer(start) > SPI_WAIT_TIMEOUT) {
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printf("SPI TXS timed out, status=0x%08x\n",
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readl(&priv->regs->channel[priv->cs].chstat));
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return -1;
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}
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}
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/* Write the data */
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unsigned int *tx = &priv->regs->channel[priv->cs].tx;
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if (priv->wordlen > 16)
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writel(((u32 *)txp)[i], tx);
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else if (priv->wordlen > 8)
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writel(((u16 *)txp)[i], tx);
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else
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writel(((u8 *)txp)[i], tx);
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}
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/* wait to finish of transfer */
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while ((readl(&priv->regs->channel[priv->cs].chstat) &
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(OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) !=
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(OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS))
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;
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/* Disable the channel otherwise the next immediate RX will get affected */
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omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
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if (flags & SPI_XFER_END) {
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chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(priv, chconf);
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}
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return 0;
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}
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static int omap3_spi_read(struct omap3_spi_priv *priv, unsigned int len,
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void *rxp, unsigned long flags)
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{
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int i, chconf;
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ulong start;
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chconf = readl(&priv->regs->channel[priv->cs].chconf);
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/* Enable the channel */
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omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
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chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
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chconf |= (priv->wordlen - 1) << 7;
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chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
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chconf |= OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(priv, chconf);
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writel(0, &priv->regs->channel[priv->cs].tx);
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for (i = 0; i < len; i++) {
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start = get_timer(0);
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/* Wait till RX register contains data (RXS == 1) */
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while (!(readl(&priv->regs->channel[priv->cs].chstat) &
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OMAP3_MCSPI_CHSTAT_RXS)) {
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if (get_timer(start) > SPI_WAIT_TIMEOUT) {
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printf("SPI RXS timed out, status=0x%08x\n",
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readl(&priv->regs->channel[priv->cs].chstat));
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return -1;
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}
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}
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/* Disable the channel to prevent furher receiving */
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if (i == (len - 1))
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omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
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/* Read the data */
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unsigned int *rx = &priv->regs->channel[priv->cs].rx;
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if (priv->wordlen > 16)
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((u32 *)rxp)[i] = readl(rx);
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else if (priv->wordlen > 8)
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((u16 *)rxp)[i] = (u16)readl(rx);
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else
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((u8 *)rxp)[i] = (u8)readl(rx);
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}
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if (flags & SPI_XFER_END) {
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chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(priv, chconf);
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}
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return 0;
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}
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/*McSPI Transmit Receive Mode*/
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static int omap3_spi_txrx(struct omap3_spi_priv *priv, unsigned int len,
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const void *txp, void *rxp, unsigned long flags)
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{
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ulong start;
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int chconf, i = 0;
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chconf = readl(&priv->regs->channel[priv->cs].chconf);
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/*Enable SPI channel*/
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omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
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/*set TRANSMIT-RECEIVE Mode*/
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chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
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chconf |= (priv->wordlen - 1) << 7;
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chconf |= OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(priv, chconf);
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/*Shift in and out 1 byte at time*/
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for (i=0; i < len; i++){
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/* Write: wait for TX empty (TXS == 1)*/
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start = get_timer(0);
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while (!(readl(&priv->regs->channel[priv->cs].chstat) &
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OMAP3_MCSPI_CHSTAT_TXS)) {
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if (get_timer(start) > SPI_WAIT_TIMEOUT) {
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printf("SPI TXS timed out, status=0x%08x\n",
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readl(&priv->regs->channel[priv->cs].chstat));
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return -1;
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}
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}
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/* Write the data */
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unsigned int *tx = &priv->regs->channel[priv->cs].tx;
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if (priv->wordlen > 16)
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writel(((u32 *)txp)[i], tx);
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else if (priv->wordlen > 8)
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writel(((u16 *)txp)[i], tx);
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else
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writel(((u8 *)txp)[i], tx);
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/*Read: wait for RX containing data (RXS == 1)*/
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start = get_timer(0);
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while (!(readl(&priv->regs->channel[priv->cs].chstat) &
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OMAP3_MCSPI_CHSTAT_RXS)) {
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if (get_timer(start) > SPI_WAIT_TIMEOUT) {
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printf("SPI RXS timed out, status=0x%08x\n",
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readl(&priv->regs->channel[priv->cs].chstat));
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return -1;
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}
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}
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/* Read the data */
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unsigned int *rx = &priv->regs->channel[priv->cs].rx;
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if (priv->wordlen > 16)
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((u32 *)rxp)[i] = readl(rx);
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else if (priv->wordlen > 8)
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((u16 *)rxp)[i] = (u16)readl(rx);
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else
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((u8 *)rxp)[i] = (u8)readl(rx);
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}
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/* Disable the channel */
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omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
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/*if transfer must be terminated disable the channel*/
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if (flags & SPI_XFER_END) {
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chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(priv, chconf);
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}
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return 0;
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}
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static int _spi_xfer(struct omap3_spi_priv *priv, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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unsigned int len;
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int ret = -1;
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if (priv->wordlen < 4 || priv->wordlen > 32) {
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printf("omap3_spi: invalid wordlen %d\n", priv->wordlen);
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return -1;
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}
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if (bitlen % priv->wordlen)
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return -1;
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len = bitlen / priv->wordlen;
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if (bitlen == 0) { /* only change CS */
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int chconf = readl(&priv->regs->channel[priv->cs].chconf);
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if (flags & SPI_XFER_BEGIN) {
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omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
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chconf |= OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(priv, chconf);
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}
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if (flags & SPI_XFER_END) {
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chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(priv, chconf);
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omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
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}
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ret = 0;
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} else {
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if (dout != NULL && din != NULL)
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ret = omap3_spi_txrx(priv, len, dout, din, flags);
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else if (dout != NULL)
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ret = omap3_spi_write(priv, len, dout, flags);
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else if (din != NULL)
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ret = omap3_spi_read(priv, len, din, flags);
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}
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return ret;
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}
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static void _omap3_spi_set_speed(struct omap3_spi_priv *priv)
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{
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uint32_t confr, div = 0;
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confr = readl(&priv->regs->channel[priv->cs].chconf);
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/* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
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if (priv->freq) {
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while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
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> priv->freq)
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div++;
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} else {
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div = 0xC;
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}
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/* set clock divisor */
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confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
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confr |= div << 2;
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omap3_spi_write_chconf(priv, confr);
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}
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static void _omap3_spi_set_mode(struct omap3_spi_priv *priv)
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{
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uint32_t confr;
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confr = readl(&priv->regs->channel[priv->cs].chconf);
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/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
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* REVISIT: this controller could support SPI_3WIRE mode.
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*/
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if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
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confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
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confr |= OMAP3_MCSPI_CHCONF_DPE0;
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} else {
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confr &= ~OMAP3_MCSPI_CHCONF_DPE0;
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confr |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
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}
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/* set SPI mode 0..3 */
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confr &= ~(OMAP3_MCSPI_CHCONF_POL | OMAP3_MCSPI_CHCONF_PHA);
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if (priv->mode & SPI_CPHA)
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confr |= OMAP3_MCSPI_CHCONF_PHA;
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if (priv->mode & SPI_CPOL)
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confr |= OMAP3_MCSPI_CHCONF_POL;
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/* set chipselect polarity; manage with FORCE */
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if (!(priv->mode & SPI_CS_HIGH))
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confr |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
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else
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confr &= ~OMAP3_MCSPI_CHCONF_EPOL;
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/* Transmit & receive mode */
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confr &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
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omap3_spi_write_chconf(priv, confr);
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}
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static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv)
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{
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unsigned int confr;
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/* McSPI individual channel configuration */
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confr = readl(&priv->regs->channel[priv->wordlen].chconf);
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/* wordlength */
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confr &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
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confr |= (priv->wordlen - 1) << 7;
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omap3_spi_write_chconf(priv, confr);
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}
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static void spi_reset(struct mcspi *regs)
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{
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unsigned int tmp;
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writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, ®s->sysconfig);
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do {
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tmp = readl(®s->sysstatus);
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} while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
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writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
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OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
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OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, ®s->sysconfig);
|
|
|
|
writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, ®s->wakeupenable);
|
|
}
|
|
|
|
static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv)
|
|
{
|
|
unsigned int conf;
|
|
|
|
spi_reset(priv->regs);
|
|
|
|
/*
|
|
* setup when switching from (reset default) slave mode
|
|
* to single-channel master mode
|
|
*/
|
|
conf = readl(&priv->regs->modulctrl);
|
|
conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS);
|
|
conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
|
|
|
|
writel(conf, &priv->regs->modulctrl);
|
|
}
|
|
|
|
#ifndef CONFIG_DM_SPI
|
|
|
|
static inline struct omap3_spi_priv *to_omap3_spi(struct spi_slave *slave)
|
|
{
|
|
return container_of(slave, struct omap3_spi_priv, slave);
|
|
}
|
|
|
|
void spi_init(void)
|
|
{
|
|
/* do nothing */
|
|
}
|
|
|
|
void spi_free_slave(struct spi_slave *slave)
|
|
{
|
|
struct omap3_spi_priv *priv = to_omap3_spi(slave);
|
|
|
|
free(priv);
|
|
}
|
|
|
|
int spi_claim_bus(struct spi_slave *slave)
|
|
{
|
|
struct omap3_spi_priv *priv = to_omap3_spi(slave);
|
|
|
|
_omap3_spi_claim_bus(priv);
|
|
_omap3_spi_set_wordlen(priv);
|
|
_omap3_spi_set_mode(priv);
|
|
_omap3_spi_set_speed(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void spi_release_bus(struct spi_slave *slave)
|
|
{
|
|
struct omap3_spi_priv *priv = to_omap3_spi(slave);
|
|
|
|
/* Reset the SPI hardware */
|
|
spi_reset(priv->regs);
|
|
}
|
|
|
|
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
|
|
unsigned int max_hz, unsigned int mode)
|
|
{
|
|
struct omap3_spi_priv *priv;
|
|
struct mcspi *regs;
|
|
|
|
/*
|
|
* OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
|
|
* with different number of chip selects (CS, channels):
|
|
* McSPI1 has 4 CS (bus 0, cs 0 - 3)
|
|
* McSPI2 has 2 CS (bus 1, cs 0 - 1)
|
|
* McSPI3 has 2 CS (bus 2, cs 0 - 1)
|
|
* McSPI4 has 1 CS (bus 3, cs 0)
|
|
*/
|
|
|
|
switch (bus) {
|
|
case 0:
|
|
regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
|
|
break;
|
|
#ifdef OMAP3_MCSPI2_BASE
|
|
case 1:
|
|
regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
|
|
break;
|
|
#endif
|
|
#ifdef OMAP3_MCSPI3_BASE
|
|
case 2:
|
|
regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
|
|
break;
|
|
#endif
|
|
#ifdef OMAP3_MCSPI4_BASE
|
|
case 3:
|
|
regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
|
|
break;
|
|
#endif
|
|
default:
|
|
printf("SPI error: unsupported bus %i. Supported busses 0 - 3\n", bus);
|
|
return NULL;
|
|
}
|
|
|
|
if (((bus == 0) && (cs > 3)) ||
|
|
((bus == 1) && (cs > 1)) ||
|
|
((bus == 2) && (cs > 1)) ||
|
|
((bus == 3) && (cs > 0))) {
|
|
printf("SPI error: unsupported chip select %i on bus %i\n", cs, bus);
|
|
return NULL;
|
|
}
|
|
|
|
if (max_hz > OMAP3_MCSPI_MAX_FREQ) {
|
|
printf("SPI error: unsupported frequency %i Hz. Max frequency is 48 MHz\n",
|
|
max_hz);
|
|
return NULL;
|
|
}
|
|
|
|
if (mode > SPI_MODE_3) {
|
|
printf("SPI error: unsupported SPI mode %i\n", mode);
|
|
return NULL;
|
|
}
|
|
|
|
priv = spi_alloc_slave(struct omap3_spi_priv, bus, cs);
|
|
if (!priv) {
|
|
printf("SPI error: malloc of SPI structure failed\n");
|
|
return NULL;
|
|
}
|
|
|
|
priv->regs = regs;
|
|
priv->cs = cs;
|
|
priv->freq = max_hz;
|
|
priv->mode = mode;
|
|
priv->wordlen = priv->slave.wordlen;
|
|
#if 0
|
|
/* Please migrate to DM_SPI support for this feature. */
|
|
priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
|
|
#endif
|
|
|
|
return &priv->slave;
|
|
}
|
|
|
|
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
|
const void *dout, void *din, unsigned long flags)
|
|
{
|
|
struct omap3_spi_priv *priv = to_omap3_spi(slave);
|
|
|
|
return _spi_xfer(priv, bitlen, dout, din, flags);
|
|
}
|
|
|
|
#else
|
|
|
|
static int omap3_spi_claim_bus(struct udevice *dev)
|
|
{
|
|
struct udevice *bus = dev->parent;
|
|
struct omap3_spi_priv *priv = dev_get_priv(bus);
|
|
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
|
|
|
|
priv->cs = slave_plat->cs;
|
|
_omap3_spi_claim_bus(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap3_spi_release_bus(struct udevice *dev)
|
|
{
|
|
struct udevice *bus = dev->parent;
|
|
struct omap3_spi_priv *priv = dev_get_priv(bus);
|
|
|
|
/* Reset the SPI hardware */
|
|
spi_reset(priv->regs);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap3_spi_set_wordlen(struct udevice *dev, unsigned int wordlen)
|
|
{
|
|
struct udevice *bus = dev->parent;
|
|
struct omap3_spi_priv *priv = dev_get_priv(bus);
|
|
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
|
|
|
|
priv->cs = slave_plat->cs;
|
|
priv->wordlen = wordlen;
|
|
_omap3_spi_set_wordlen(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap3_spi_probe(struct udevice *dev)
|
|
{
|
|
struct omap3_spi_priv *priv = dev_get_priv(dev);
|
|
const void *blob = gd->fdt_blob;
|
|
int node = dev_of_offset(dev);
|
|
|
|
struct omap2_mcspi_platform_config* data =
|
|
(struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
|
|
|
|
priv->regs = (struct mcspi *)(devfdt_get_addr(dev) + data->regs_offset);
|
|
if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in"))
|
|
priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
|
|
else
|
|
priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
|
|
priv->wordlen = SPI_DEFAULT_WORDLEN;
|
|
return 0;
|
|
}
|
|
|
|
static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen,
|
|
const void *dout, void *din, unsigned long flags)
|
|
{
|
|
struct udevice *bus = dev->parent;
|
|
struct omap3_spi_priv *priv = dev_get_priv(bus);
|
|
|
|
return _spi_xfer(priv, bitlen, dout, din, flags);
|
|
}
|
|
|
|
static int omap3_spi_set_speed(struct udevice *dev, unsigned int speed)
|
|
{
|
|
struct udevice *bus = dev->parent;
|
|
struct omap3_spi_priv *priv = dev_get_priv(bus);
|
|
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
|
|
|
|
priv->cs = slave_plat->cs;
|
|
priv->freq = slave_plat->max_hz;
|
|
_omap3_spi_set_speed(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap3_spi_set_mode(struct udevice *dev, uint mode)
|
|
{
|
|
struct udevice *bus = dev->parent;
|
|
struct omap3_spi_priv *priv = dev_get_priv(bus);
|
|
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
|
|
|
|
priv->cs = slave_plat->cs;
|
|
priv->mode = slave_plat->mode;
|
|
_omap3_spi_set_mode(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_spi_ops omap3_spi_ops = {
|
|
.claim_bus = omap3_spi_claim_bus,
|
|
.release_bus = omap3_spi_release_bus,
|
|
.set_wordlen = omap3_spi_set_wordlen,
|
|
.xfer = omap3_spi_xfer,
|
|
.set_speed = omap3_spi_set_speed,
|
|
.set_mode = omap3_spi_set_mode,
|
|
/*
|
|
* cs_info is not needed, since we require all chip selects to be
|
|
* in the device tree explicitly
|
|
*/
|
|
};
|
|
|
|
static struct omap2_mcspi_platform_config omap2_pdata = {
|
|
.regs_offset = 0,
|
|
};
|
|
|
|
static struct omap2_mcspi_platform_config omap4_pdata = {
|
|
.regs_offset = OMAP4_MCSPI_REG_OFFSET,
|
|
};
|
|
|
|
static const struct udevice_id omap3_spi_ids[] = {
|
|
{ .compatible = "ti,omap2-mcspi", .data = (ulong)&omap2_pdata },
|
|
{ .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(omap3_spi) = {
|
|
.name = "omap3_spi",
|
|
.id = UCLASS_SPI,
|
|
.of_match = omap3_spi_ids,
|
|
.probe = omap3_spi_probe,
|
|
.ops = &omap3_spi_ops,
|
|
.priv_auto_alloc_size = sizeof(struct omap3_spi_priv),
|
|
};
|
|
#endif
|