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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
192 lines
5.2 KiB
C
192 lines
5.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include "../pinctrl/renesas/sh_pfc.h"
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#define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
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#define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */
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#define GPIO_OUTDT 0x08 /* General Output Register */
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#define GPIO_INDT 0x0c /* General Input Register */
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#define GPIO_INTDT 0x10 /* Interrupt Display Register */
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#define GPIO_INTCLR 0x14 /* Interrupt Clear Register */
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#define GPIO_INTMSK 0x18 /* Interrupt Mask Register */
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#define GPIO_MSKCLR 0x1c /* Interrupt Mask Clear Register */
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#define GPIO_POSNEG 0x20 /* Positive/Negative Logic Select Register */
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#define GPIO_EDGLEVEL 0x24 /* Edge/level Select Register */
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#define GPIO_FILONOFF 0x28 /* Chattering Prevention On/Off Register */
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#define GPIO_BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
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#define RCAR_MAX_GPIO_PER_BANK 32
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DECLARE_GLOBAL_DATA_PTR;
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struct rcar_gpio_priv {
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void __iomem *regs;
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int pfc_offset;
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};
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static int rcar_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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struct rcar_gpio_priv *priv = dev_get_priv(dev);
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const u32 bit = BIT(offset);
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/*
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* Testing on r8a7790 shows that INDT does not show correct pin state
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* when configured as output, so use OUTDT in case of output pins.
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*/
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if (readl(priv->regs + GPIO_INOUTSEL) & bit)
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return !!(readl(priv->regs + GPIO_OUTDT) & bit);
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else
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return !!(readl(priv->regs + GPIO_INDT) & bit);
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}
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static int rcar_gpio_set_value(struct udevice *dev, unsigned offset,
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int value)
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{
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struct rcar_gpio_priv *priv = dev_get_priv(dev);
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if (value)
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setbits_le32(priv->regs + GPIO_OUTDT, BIT(offset));
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else
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clrbits_le32(priv->regs + GPIO_OUTDT, BIT(offset));
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return 0;
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}
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static void rcar_gpio_set_direction(void __iomem *regs, unsigned offset,
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bool output)
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{
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/*
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* follow steps in the GPIO documentation for
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* "Setting General Output Mode" and
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* "Setting General Input Mode"
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*/
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/* Configure postive logic in POSNEG */
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clrbits_le32(regs + GPIO_POSNEG, BIT(offset));
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/* Select "General Input/Output Mode" in IOINTSEL */
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clrbits_le32(regs + GPIO_IOINTSEL, BIT(offset));
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/* Select Input Mode or Output Mode in INOUTSEL */
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if (output)
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setbits_le32(regs + GPIO_INOUTSEL, BIT(offset));
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else
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clrbits_le32(regs + GPIO_INOUTSEL, BIT(offset));
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}
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static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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struct rcar_gpio_priv *priv = dev_get_priv(dev);
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rcar_gpio_set_direction(priv->regs, offset, false);
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return 0;
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}
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static int rcar_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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struct rcar_gpio_priv *priv = dev_get_priv(dev);
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/* write GPIO value to output before selecting output mode of pin */
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rcar_gpio_set_value(dev, offset, value);
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rcar_gpio_set_direction(priv->regs, offset, true);
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return 0;
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}
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static int rcar_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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struct rcar_gpio_priv *priv = dev_get_priv(dev);
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if (readl(priv->regs + GPIO_INOUTSEL) & BIT(offset))
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return GPIOF_OUTPUT;
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else
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return GPIOF_INPUT;
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}
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static int rcar_gpio_request(struct udevice *dev, unsigned offset,
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const char *label)
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{
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struct rcar_gpio_priv *priv = dev_get_priv(dev);
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struct udevice *pctldev;
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int ret;
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ret = uclass_get_device(UCLASS_PINCTRL, 0, &pctldev);
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if (ret)
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return ret;
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return sh_pfc_config_mux_for_gpio(pctldev, priv->pfc_offset + offset);
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}
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static const struct dm_gpio_ops rcar_gpio_ops = {
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.request = rcar_gpio_request,
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.direction_input = rcar_gpio_direction_input,
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.direction_output = rcar_gpio_direction_output,
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.get_value = rcar_gpio_get_value,
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.set_value = rcar_gpio_set_value,
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.get_function = rcar_gpio_get_function,
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};
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static int rcar_gpio_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct rcar_gpio_priv *priv = dev_get_priv(dev);
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struct fdtdec_phandle_args args;
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struct clk clk;
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int node = dev_of_offset(dev);
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int ret;
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priv->regs = (void __iomem *)devfdt_get_addr(dev);
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uc_priv->bank_name = dev->name;
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ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
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NULL, 3, 0, &args);
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priv->pfc_offset = ret == 0 ? args.args[1] : -1;
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uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0) {
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dev_err(dev, "Failed to get GPIO bank clock\n");
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return ret;
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}
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ret = clk_enable(&clk);
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clk_free(&clk);
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if (ret) {
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dev_err(dev, "Failed to enable GPIO bank clock\n");
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return ret;
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}
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return 0;
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}
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static const struct udevice_id rcar_gpio_ids[] = {
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{ .compatible = "renesas,gpio-r8a7795" },
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{ .compatible = "renesas,gpio-r8a7796" },
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{ .compatible = "renesas,gpio-r8a77965" },
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{ .compatible = "renesas,gpio-r8a77970" },
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{ .compatible = "renesas,gpio-r8a77995" },
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{ .compatible = "renesas,rcar-gen2-gpio" },
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{ .compatible = "renesas,rcar-gen3-gpio" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(rcar_gpio) = {
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.name = "rcar-gpio",
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.id = UCLASS_GPIO,
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.of_match = rcar_gpio_ids,
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.ops = &rcar_gpio_ops,
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.priv_auto_alloc_size = sizeof(struct rcar_gpio_priv),
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.probe = rcar_gpio_probe,
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};
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