mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 00:18:51 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
716 lines
19 KiB
C
716 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <stm32_rcc.h>
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#include <asm/io.h>
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#include <asm/arch/stm32.h>
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#include <asm/arch/stm32_pwr.h>
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#include <dt-bindings/mfd/stm32f7-rcc.h>
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#define RCC_CR_HSION BIT(0)
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#define RCC_CR_HSEON BIT(16)
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#define RCC_CR_HSERDY BIT(17)
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#define RCC_CR_HSEBYP BIT(18)
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#define RCC_CR_CSSON BIT(19)
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#define RCC_CR_PLLON BIT(24)
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#define RCC_CR_PLLRDY BIT(25)
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#define RCC_CR_PLLSAION BIT(28)
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#define RCC_CR_PLLSAIRDY BIT(29)
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#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
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#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
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#define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
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#define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
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#define RCC_PLLCFGR_PLLSRC BIT(22)
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#define RCC_PLLCFGR_PLLM_SHIFT 0
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#define RCC_PLLCFGR_PLLN_SHIFT 6
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#define RCC_PLLCFGR_PLLP_SHIFT 16
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#define RCC_PLLCFGR_PLLQ_SHIFT 24
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#define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
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#define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
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#define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
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#define RCC_CFGR_SW0 BIT(0)
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#define RCC_CFGR_SW1 BIT(1)
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#define RCC_CFGR_SW_MASK GENMASK(1, 0)
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#define RCC_CFGR_SW_HSI 0
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#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
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#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
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#define RCC_CFGR_SWS0 BIT(2)
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#define RCC_CFGR_SWS1 BIT(3)
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#define RCC_CFGR_SWS_MASK GENMASK(3, 2)
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#define RCC_CFGR_SWS_HSI 0
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#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
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#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
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#define RCC_CFGR_HPRE_SHIFT 4
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#define RCC_CFGR_PPRE1_SHIFT 10
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#define RCC_CFGR_PPRE2_SHIFT 13
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#define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6)
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#define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16)
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#define RCC_PLLSAICFGR_PLLSAIQ_MASK GENMASK(27, 24)
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#define RCC_PLLSAICFGR_PLLSAIR_MASK GENMASK(30, 28)
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#define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
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#define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
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#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24
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#define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28
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#define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16)
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#define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
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#define RCC_PLLSAICFGR_PLLSAIR_3 BIT(29) | BIT(28)
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#define RCC_DCKCFGRX_TIMPRE BIT(24)
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#define RCC_DCKCFGRX_CK48MSEL BIT(27)
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#define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
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#define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
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#define RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16
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#define RCC_DCKCFGR_PLLSAIDIVR_MASK GENMASK(17, 16)
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#define RCC_DCKCFGR_PLLSAIDIVR_2 0
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/*
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* RCC AHB1ENR specific definitions
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*/
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#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
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#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
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#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
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/*
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* RCC APB1ENR specific definitions
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*/
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#define RCC_APB1ENR_TIM2EN BIT(0)
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#define RCC_APB1ENR_PWREN BIT(28)
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/*
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* RCC APB2ENR specific definitions
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*/
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#define RCC_APB2ENR_SYSCFGEN BIT(14)
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#define RCC_APB2ENR_SAI1EN BIT(22)
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enum pllsai_div {
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PLLSAIP,
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PLLSAIQ,
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PLLSAIR,
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};
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static const struct stm32_clk_info stm32f4_clk_info = {
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/* 180 MHz */
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.sys_pll_psc = {
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.pll_n = 360,
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.pll_p = 2,
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.pll_q = 8,
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.ahb_psc = AHB_PSC_1,
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.apb1_psc = APB_PSC_4,
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.apb2_psc = APB_PSC_2,
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},
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.has_overdrive = false,
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.v2 = false,
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};
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static const struct stm32_clk_info stm32f7_clk_info = {
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/* 200 MHz */
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.sys_pll_psc = {
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.pll_n = 400,
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.pll_p = 2,
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.pll_q = 8,
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.ahb_psc = AHB_PSC_1,
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.apb1_psc = APB_PSC_4,
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.apb2_psc = APB_PSC_2,
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},
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.has_overdrive = true,
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.v2 = true,
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};
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struct stm32_clk {
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struct stm32_rcc_regs *base;
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struct stm32_pwr_regs *pwr_regs;
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struct stm32_clk_info info;
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unsigned long hse_rate;
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};
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#ifdef CONFIG_VIDEO_STM32
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static const u8 plldivr_table[] = { 0, 0, 2, 3, 4, 5, 6, 7 };
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#endif
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static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 };
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static int configure_clocks(struct udevice *dev)
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{
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struct stm32_clk *priv = dev_get_priv(dev);
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struct stm32_rcc_regs *regs = priv->base;
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struct stm32_pwr_regs *pwr = priv->pwr_regs;
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struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
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/* Reset RCC configuration */
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setbits_le32(®s->cr, RCC_CR_HSION);
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writel(0, ®s->cfgr); /* Reset CFGR */
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clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON
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| RCC_CR_PLLON | RCC_CR_PLLSAION));
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writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */
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clrbits_le32(®s->cr, RCC_CR_HSEBYP);
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writel(0, ®s->cir); /* Disable all interrupts */
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/* Configure for HSE+PLL operation */
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setbits_le32(®s->cr, RCC_CR_HSEON);
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while (!(readl(®s->cr) & RCC_CR_HSERDY))
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;
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setbits_le32(®s->cfgr, ((
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sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT)
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| (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT)
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| (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
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/* Configure the main PLL */
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setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
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clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
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sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT);
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clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
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sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT);
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clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
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((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
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clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
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sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
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/* configure SDMMC clock */
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if (priv->info.v2) { /*stm32f7 case */
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/* select PLLQ as 48MHz clock source */
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clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
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/* select 48MHz as SDMMC1 clock source */
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clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
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/* select 48MHz as SDMMC2 clock source */
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clrbits_le32(®s->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
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} else { /* stm32f4 case */
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/* select PLLQ as 48MHz clock source */
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clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
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/* select 48MHz as SDMMC1 clock source */
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clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
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}
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#ifdef CONFIG_VIDEO_STM32
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/*
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* Configure the SAI PLL to generate LTDC pixel clock
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*/
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clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
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RCC_PLLSAICFGR_PLLSAIR_3);
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clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIN_MASK,
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195 << RCC_PLLSAICFGR_PLLSAIN_SHIFT);
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clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
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RCC_DCKCFGR_PLLSAIDIVR_2 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
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#endif
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/* Enable the main PLL */
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setbits_le32(®s->cr, RCC_CR_PLLON);
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while (!(readl(®s->cr) & RCC_CR_PLLRDY))
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;
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#ifdef CONFIG_VIDEO_STM32
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/* Enable the SAI PLL */
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setbits_le32(®s->cr, RCC_CR_PLLSAION);
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while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY))
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;
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#endif
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setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
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if (priv->info.has_overdrive) {
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/*
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* Enable high performance mode
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* System frequency up to 200 MHz
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*/
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setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
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/* Infinite wait! */
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while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
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;
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/* Enable the Over-drive switch */
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setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
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/* Infinite wait! */
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while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
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;
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}
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stm32_flash_latency_cfg(5);
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clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
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setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL);
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while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) !=
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RCC_CFGR_SWS_PLL)
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;
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#ifdef CONFIG_ETH_DESIGNWARE
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/* gate the SYSCFG clock, needed to set RMII ethernet interface */
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setbits_le32(®s->apb2enr, RCC_APB2ENR_SYSCFGEN);
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#endif
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return 0;
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}
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static bool stm32_clk_get_ck48msel(struct stm32_clk *priv)
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{
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struct stm32_rcc_regs *regs = priv->base;
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if (priv->info.v2) /*stm32f7 case */
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return readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
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else
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return readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
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}
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static unsigned long stm32_clk_get_pllsai_vco_rate(struct stm32_clk *priv)
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{
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struct stm32_rcc_regs *regs = priv->base;
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u16 pllm, pllsain;
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pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
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pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK)
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>> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
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return ((priv->hse_rate / pllm) * pllsain);
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}
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static unsigned long stm32_clk_get_pllsai_rate(struct stm32_clk *priv,
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enum pllsai_div output)
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{
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struct stm32_rcc_regs *regs = priv->base;
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u16 pll_div_output;
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switch (output) {
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case PLLSAIP:
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pll_div_output = ((((readl(®s->pllsaicfgr)
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& RCC_PLLSAICFGR_PLLSAIP_MASK)
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>> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
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break;
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case PLLSAIQ:
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pll_div_output = (readl(®s->pllsaicfgr)
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& RCC_PLLSAICFGR_PLLSAIQ_MASK)
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>> RCC_PLLSAICFGR_PLLSAIQ_SHIFT;
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break;
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case PLLSAIR:
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pll_div_output = (readl(®s->pllsaicfgr)
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& RCC_PLLSAICFGR_PLLSAIR_MASK)
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>> RCC_PLLSAICFGR_PLLSAIR_SHIFT;
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break;
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default:
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pr_err("incorrect PLLSAI output %d\n", output);
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return -EINVAL;
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}
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return (stm32_clk_get_pllsai_vco_rate(priv) / pll_div_output);
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}
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static bool stm32_get_timpre(struct stm32_clk *priv)
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{
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struct stm32_rcc_regs *regs = priv->base;
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u32 val;
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if (priv->info.v2) /*stm32f7 case */
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val = readl(®s->dckcfgr2);
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else
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val = readl(®s->dckcfgr);
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/* get timer prescaler */
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return !!(val & RCC_DCKCFGRX_TIMPRE);
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}
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static u32 stm32_get_hclk_rate(struct stm32_rcc_regs *regs, u32 sysclk)
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{
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u8 shift;
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/* Prescaler table lookups for clock computation */
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u8 ahb_psc_table[16] = {
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0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
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};
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shift = ahb_psc_table[(
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(readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK)
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>> RCC_CFGR_HPRE_SHIFT)];
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return sysclk >> shift;
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};
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static u8 stm32_get_apb_shift(struct stm32_rcc_regs *regs, enum apb apb)
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{
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/* Prescaler table lookups for clock computation */
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u8 apb_psc_table[8] = {
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0, 0, 0, 0, 1, 2, 3, 4
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};
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if (apb == APB1)
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return apb_psc_table[(
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(readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK)
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>> RCC_CFGR_PPRE1_SHIFT)];
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else /* APB2 */
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return apb_psc_table[(
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(readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK)
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>> RCC_CFGR_PPRE2_SHIFT)];
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};
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static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
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enum apb apb)
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{
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struct stm32_rcc_regs *regs = priv->base;
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u8 shift = stm32_get_apb_shift(regs, apb);
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if (stm32_get_timpre(priv))
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/*
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* if APB prescaler is configured to a
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* division factor of 1, 2 or 4
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*/
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switch (shift) {
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case 0:
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case 1:
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case 2:
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return stm32_get_hclk_rate(regs, sysclk);
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default:
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return (sysclk >> shift) * 4;
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}
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else
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/*
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* if APB prescaler is configured to a
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* division factor of 1
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*/
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if (shift == 0)
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return sysclk;
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else
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return (sysclk >> shift) * 2;
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};
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static ulong stm32_clk_get_rate(struct clk *clk)
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{
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struct stm32_clk *priv = dev_get_priv(clk->dev);
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struct stm32_rcc_regs *regs = priv->base;
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u32 sysclk = 0;
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u32 vco;
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u32 sdmmcxsel_bit;
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u32 saidivr;
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u32 pllsai_rate;
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u16 pllm, plln, pllp, pllq;
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if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) ==
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RCC_CFGR_SWS_PLL) {
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pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
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plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
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>> RCC_PLLCFGR_PLLN_SHIFT);
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pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
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>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
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pllq = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
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>> RCC_PLLCFGR_PLLQ_SHIFT);
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vco = (priv->hse_rate / pllm) * plln;
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sysclk = vco / pllp;
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} else {
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return -EINVAL;
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}
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switch (clk->id) {
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/*
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* AHB CLOCK: 3 x 32 bits consecutive registers are used :
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* AHB1, AHB2 and AHB3
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*/
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case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
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return stm32_get_hclk_rate(regs, sysclk);
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/* APB1 CLOCK */
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case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
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/* For timer clock, an additionnal prescaler is used*/
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switch (clk->id) {
|
|
case STM32F7_APB1_CLOCK(TIM2):
|
|
case STM32F7_APB1_CLOCK(TIM3):
|
|
case STM32F7_APB1_CLOCK(TIM4):
|
|
case STM32F7_APB1_CLOCK(TIM5):
|
|
case STM32F7_APB1_CLOCK(TIM6):
|
|
case STM32F7_APB1_CLOCK(TIM7):
|
|
case STM32F7_APB1_CLOCK(TIM12):
|
|
case STM32F7_APB1_CLOCK(TIM13):
|
|
case STM32F7_APB1_CLOCK(TIM14):
|
|
return stm32_get_timer_rate(priv, sysclk, APB1);
|
|
}
|
|
return (sysclk >> stm32_get_apb_shift(regs, APB1));
|
|
|
|
/* APB2 CLOCK */
|
|
case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(DSI):
|
|
switch (clk->id) {
|
|
/*
|
|
* particular case for SDMMC1 and SDMMC2 :
|
|
* 48Mhz source clock can be from main PLL or from
|
|
* PLLSAIP
|
|
*/
|
|
case STM32F7_APB2_CLOCK(SDMMC1):
|
|
case STM32F7_APB2_CLOCK(SDMMC2):
|
|
if (clk->id == STM32F7_APB2_CLOCK(SDMMC1))
|
|
sdmmcxsel_bit = RCC_DCKCFGRX_SDMMC1SEL;
|
|
else
|
|
sdmmcxsel_bit = RCC_DCKCFGR2_SDMMC2SEL;
|
|
|
|
if (readl(®s->dckcfgr2) & sdmmcxsel_bit)
|
|
/* System clock is selected as SDMMC1 clock */
|
|
return sysclk;
|
|
/*
|
|
* 48 MHz can be generated by either PLLSAIP
|
|
* or by PLLQ depending of CK48MSEL bit of RCC_DCKCFGR
|
|
*/
|
|
if (stm32_clk_get_ck48msel(priv))
|
|
return stm32_clk_get_pllsai_rate(priv, PLLSAIP);
|
|
else
|
|
return (vco / pllq);
|
|
break;
|
|
|
|
/* For timer clock, an additionnal prescaler is used*/
|
|
case STM32F7_APB2_CLOCK(TIM1):
|
|
case STM32F7_APB2_CLOCK(TIM8):
|
|
case STM32F7_APB2_CLOCK(TIM9):
|
|
case STM32F7_APB2_CLOCK(TIM10):
|
|
case STM32F7_APB2_CLOCK(TIM11):
|
|
return stm32_get_timer_rate(priv, sysclk, APB2);
|
|
break;
|
|
|
|
/* particular case for LTDC clock */
|
|
case STM32F7_APB2_CLOCK(LTDC):
|
|
saidivr = readl(®s->dckcfgr);
|
|
saidivr = (saidivr & RCC_DCKCFGR_PLLSAIDIVR_MASK)
|
|
>> RCC_DCKCFGR_PLLSAIDIVR_SHIFT;
|
|
pllsai_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
|
|
|
|
return pllsai_rate / pllsaidivr_table[saidivr];
|
|
}
|
|
return (sysclk >> stm32_get_apb_shift(regs, APB2));
|
|
|
|
default:
|
|
pr_err("clock index %ld out of range\n", clk->id);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static ulong stm32_set_rate(struct clk *clk, ulong rate)
|
|
{
|
|
#ifdef CONFIG_VIDEO_STM32
|
|
struct stm32_clk *priv = dev_get_priv(clk->dev);
|
|
struct stm32_rcc_regs *regs = priv->base;
|
|
u32 pllsair_rate, pllsai_vco_rate, current_rate;
|
|
u32 best_div, best_diff, diff;
|
|
u16 div;
|
|
u8 best_plldivr, best_pllsaidivr;
|
|
u8 i, j;
|
|
bool found = false;
|
|
|
|
/* Only set_rate for LTDC clock is implemented */
|
|
if (clk->id != STM32F7_APB2_CLOCK(LTDC)) {
|
|
pr_err("set_rate not implemented for clock index %ld\n",
|
|
clk->id);
|
|
return 0;
|
|
}
|
|
|
|
if (rate == stm32_clk_get_rate(clk))
|
|
/* already set to requested rate */
|
|
return rate;
|
|
|
|
/* get the current PLLSAIR output freq */
|
|
pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
|
|
best_div = pllsair_rate / rate;
|
|
|
|
/* look into pllsaidivr_table if this divider is available*/
|
|
for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
|
|
if (best_div == pllsaidivr_table[i]) {
|
|
/* set pll_saidivr with found value */
|
|
clrsetbits_le32(®s->dckcfgr,
|
|
RCC_DCKCFGR_PLLSAIDIVR_MASK,
|
|
pllsaidivr_table[i]);
|
|
return rate;
|
|
}
|
|
|
|
/*
|
|
* As no pllsaidivr value is suitable to obtain requested freq,
|
|
* test all combination of pllsaidivr * pllsair and find the one
|
|
* which give freq closest to requested rate.
|
|
*/
|
|
|
|
pllsai_vco_rate = stm32_clk_get_pllsai_vco_rate(priv);
|
|
best_diff = ULONG_MAX;
|
|
best_pllsaidivr = 0;
|
|
best_plldivr = 0;
|
|
/*
|
|
* start at index 2 of plldivr_table as divider value at index 0
|
|
* and 1 are 0)
|
|
*/
|
|
for (i = 2; i < sizeof(plldivr_table); i++) {
|
|
for (j = 0; j < sizeof(pllsaidivr_table); j++) {
|
|
div = plldivr_table[i] * pllsaidivr_table[j];
|
|
current_rate = pllsai_vco_rate / div;
|
|
/* perfect combination is found ? */
|
|
if (current_rate == rate) {
|
|
best_pllsaidivr = j;
|
|
best_plldivr = i;
|
|
found = true;
|
|
break;
|
|
}
|
|
|
|
diff = (current_rate > rate) ?
|
|
current_rate - rate : rate - current_rate;
|
|
|
|
/* found a better combination ? */
|
|
if (diff < best_diff) {
|
|
best_diff = diff;
|
|
best_pllsaidivr = j;
|
|
best_plldivr = i;
|
|
}
|
|
}
|
|
|
|
if (found)
|
|
break;
|
|
}
|
|
|
|
/* Disable the SAI PLL */
|
|
clrbits_le32(®s->cr, RCC_CR_PLLSAION);
|
|
|
|
/* set pll_saidivr with found value */
|
|
clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
|
|
best_pllsaidivr << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
|
|
|
|
/* set pllsair with found value */
|
|
clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
|
|
plldivr_table[best_plldivr]
|
|
<< RCC_PLLSAICFGR_PLLSAIR_SHIFT);
|
|
|
|
/* Enable the SAI PLL */
|
|
setbits_le32(®s->cr, RCC_CR_PLLSAION);
|
|
while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY))
|
|
;
|
|
|
|
div = plldivr_table[best_plldivr] * pllsaidivr_table[best_pllsaidivr];
|
|
return pllsai_vco_rate / div;
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|
|
|
|
static int stm32_clk_enable(struct clk *clk)
|
|
{
|
|
struct stm32_clk *priv = dev_get_priv(clk->dev);
|
|
struct stm32_rcc_regs *regs = priv->base;
|
|
u32 offset = clk->id / 32;
|
|
u32 bit_index = clk->id % 32;
|
|
|
|
debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
|
|
__func__, clk->id, offset, bit_index);
|
|
setbits_le32(®s->ahb1enr + offset, BIT(bit_index));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_clk_probe(struct udevice *dev)
|
|
{
|
|
struct ofnode_phandle_args args;
|
|
struct udevice *fixed_clock_dev = NULL;
|
|
struct clk clk;
|
|
int err;
|
|
|
|
debug("%s\n", __func__);
|
|
|
|
struct stm32_clk *priv = dev_get_priv(dev);
|
|
fdt_addr_t addr;
|
|
|
|
addr = dev_read_addr(dev);
|
|
if (addr == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
priv->base = (struct stm32_rcc_regs *)addr;
|
|
|
|
switch (dev_get_driver_data(dev)) {
|
|
case STM32F4:
|
|
memcpy(&priv->info, &stm32f4_clk_info,
|
|
sizeof(struct stm32_clk_info));
|
|
break;
|
|
case STM32F7:
|
|
memcpy(&priv->info, &stm32f7_clk_info,
|
|
sizeof(struct stm32_clk_info));
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* retrieve HSE frequency (external oscillator) */
|
|
err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse",
|
|
&fixed_clock_dev);
|
|
|
|
if (err) {
|
|
pr_err("Can't find fixed clock (%d)", err);
|
|
return err;
|
|
}
|
|
|
|
err = clk_request(fixed_clock_dev, &clk);
|
|
if (err) {
|
|
pr_err("Can't request %s clk (%d)", fixed_clock_dev->name,
|
|
err);
|
|
return err;
|
|
}
|
|
|
|
/*
|
|
* set pllm factor accordingly to the external oscillator
|
|
* frequency (HSE). For STM32F4 and STM32F7, we want VCO
|
|
* freq at 1MHz
|
|
* if input PLL frequency is 25Mhz, divide it by 25
|
|
*/
|
|
clk.id = 0;
|
|
priv->hse_rate = clk_get_rate(&clk);
|
|
|
|
if (priv->hse_rate < 1000000) {
|
|
pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__,
|
|
priv->hse_rate);
|
|
return -EINVAL;
|
|
}
|
|
|
|
priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000;
|
|
|
|
if (priv->info.has_overdrive) {
|
|
err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
|
|
&args);
|
|
if (err) {
|
|
debug("%s: can't find syscon device (%d)\n", __func__,
|
|
err);
|
|
return err;
|
|
}
|
|
|
|
priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
|
|
}
|
|
|
|
configure_clocks(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
|
|
{
|
|
debug("%s(clk=%p)\n", __func__, clk);
|
|
|
|
if (args->args_count != 2) {
|
|
debug("Invaild args_count: %d\n", args->args_count);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (args->args_count)
|
|
clk->id = args->args[1];
|
|
else
|
|
clk->id = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct clk_ops stm32_clk_ops = {
|
|
.of_xlate = stm32_clk_of_xlate,
|
|
.enable = stm32_clk_enable,
|
|
.get_rate = stm32_clk_get_rate,
|
|
.set_rate = stm32_set_rate,
|
|
};
|
|
|
|
U_BOOT_DRIVER(stm32fx_clk) = {
|
|
.name = "stm32fx_rcc_clock",
|
|
.id = UCLASS_CLK,
|
|
.ops = &stm32_clk_ops,
|
|
.probe = stm32_clk_probe,
|
|
.priv_auto_alloc_size = sizeof(struct stm32_clk),
|
|
.flags = DM_FLAG_PRE_RELOC,
|
|
};
|