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https://github.com/brain-hackers/u-boot-brain
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f7c32e8ece
As the old ethernet PHY is not available any more, the x600 board has been redesigned with the Micrel KSZ9031 PHY. This patch adds support to autodetect the PHY and configure the Micrel PHY correctly. Signed-off-by: Stefan Roese <sr@denx.de>
148 lines
3.7 KiB
C
148 lines
3.7 KiB
C
/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* Copyright (C) 2012 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <micrel.h>
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#include <nand.h>
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#include <netdev.h>
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#include <phy.h>
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#include <rtc.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/spr_defs.h>
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#include <asm/arch/spr_misc.h>
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#include <linux/mtd/fsmc_nand.h>
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#include "fpga.h"
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static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
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int board_init(void)
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{
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/*
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* X600 is equipped with an M41T82 RTC. This RTC has the
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* HT bit (Halt Update), which needs to be cleared upon
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* power-up. Otherwise the RTC is halted.
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*/
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rtc_reset();
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return spear_board_init(MACH_TYPE_SPEAR600);
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}
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int board_late_init(void)
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{
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/*
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* Monitor and env protection on by default
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*/
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flash_protect(FLAG_PROTECT_SET,
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CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
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CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
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2 * CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[0]);
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/* Init FPGA subsystem */
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x600_init_fpga();
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return 0;
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}
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/*
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* board_nand_init - Board specific NAND initialization
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* @nand: mtd private chip structure
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*
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* Called by nand_init_chip to initialize the board specific functions
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*/
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void board_nand_init(void)
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{
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struct misc_regs *const misc_regs_p =
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(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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struct nand_chip *nand = &nand_chip[0];
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if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
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fsmc_nand_init(nand);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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unsigned short id1, id2;
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/* check whether KSZ9031 or AR8035 has to be configured */
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id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
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id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
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if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
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/* PHY configuration for Micrel KSZ9031 */
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printf("PHY KSZ9031 detected - ");
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phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
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/* control data pad skew - devaddr = 0x02, register = 0x04 */
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ksz9031_phy_extended_write(phydev, 0x02,
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MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC,
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0x0000);
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/* rx data pad skew - devaddr = 0x02, register = 0x05 */
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ksz9031_phy_extended_write(phydev, 0x02,
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MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC,
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0x0000);
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/* tx data pad skew - devaddr = 0x02, register = 0x05 */
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ksz9031_phy_extended_write(phydev, 0x02,
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MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC,
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0x0000);
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/* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */
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ksz9031_phy_extended_write(phydev, 0x02,
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MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC,
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0x03FF);
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} else {
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/* PHY configuration for Vitesse VSC8641 */
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printf("PHY VSC8641 detected - ");
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/* Extended PHY control 1, select GMII */
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phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
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/* Software reset necessary after GMII mode selction */
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phy_reset(phydev);
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/* Enable extended page register access */
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phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
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/* 17e: Enhanced LED behavior, needs to be written twice */
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phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
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phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
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/* 16e: Enhanced LED method select */
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phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
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/* Disable extended page register access */
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phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
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/* Enable clock output pin */
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phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
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}
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int ret = 0;
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if (designware_initialize(CONFIG_SPEAR_ETHBASE,
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PHY_INTERFACE_MODE_GMII) >= 0)
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ret++;
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return ret;
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}
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