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550650ddd0
This patch removes the PPC4xx UART driver. Instead the common NS16550 driver is used, since all PPC4xx SoC's use this peripheral device. The file 4xx_uart.c now only implements the UART clock calculation function which also sets the SoC internal UART divisors. All PPC4xx board config headers are changed to use this common NS16550 driver now. Tested on these boards: acadia, canyonlands, katmai, kilauea, sequoia, zeus Signed-off-by: Stefan Roese <sr@denx.de>
73 lines
2.8 KiB
C
73 lines
2.8 KiB
C
/*
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* (C) Copyright 2010
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _PPC440GP_H_
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#define _PPC440GP_H_
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#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */
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/*
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* Some SoC specific registers (not common for all 440 SoC's)
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*/
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/* Memory mapped register */
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#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* Internal Peripherals */
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
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#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
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#define SDR0_PCI0 0x0300
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#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
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#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
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#define CNTRL_DCR_BASE 0x0b0
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#define CPC0_SYS0 (CNTRL_DCR_BASE + 0x30) /* System configuration reg 0 */
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#define CPC0_SYS1 (CNTRL_DCR_BASE + 0x31) /* System configuration reg 1 */
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#define CPC0_STRP0 (CNTRL_DCR_BASE + 0x34) /* Power-on config reg 0 (RO) */
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#define CPC0_STRP1 (CNTRL_DCR_BASE + 0x35) /* Power-on config reg 1 (RO) */
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#define CPC0_GPIO (CNTRL_DCR_BASE + 0x38) /* GPIO config reg (440GP) */
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#define CPC0_CR0 (CNTRL_DCR_BASE + 0x3b) /* Control 0 register */
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#define CPC0_CR1 (CNTRL_DCR_BASE + 0x3a) /* Control 1 register */
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#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
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#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
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#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
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#define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */
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#define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */
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#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
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#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
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#define PLLSYS0_RW_MASK 0x00000060 /* ROM width */
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#define PLLSYS0_RL_MASK 0x00000010 /* ROM location */
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#define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */
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#define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */
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#define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
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#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040)
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#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044)
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#endif /* _PPC440GP_H_ */
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