mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 19:26:16 +09:00
f0600af212
zynq-7000.dtsi include skeleton.dtsi which contains memory node with base address and size zero. If you add memory@0 node to the platform DTS in final DTB there are two memory nodes and U-Boot works with the first one (with zeros) which end up in failing in dram_init because size is zero. Platform memory node should rewrite default memory node setup from skeleton.dtsi that's why platfroms needs to also use memory as node name instead of memory@0. Reported-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
94 lines
1.3 KiB
Plaintext
94 lines
1.3 KiB
Plaintext
/*
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* Xilinx ZC770 XM010 board DTS
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*
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* Copyright (C) 2013 - 2015 Xilinx, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include "zynq-7000.dtsi"
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/ {
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compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
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model = "Xilinx Zynq";
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aliases {
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ethernet0 = &gem0;
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i2c0 = &i2c0;
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serial0 = &uart1;
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spi0 = &spi1;
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};
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chosen {
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bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
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linux,stdout-path = &uart1;
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stdout-path = &uart1;
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x40000000>;
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};
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usb_phy0: phy0 {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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};
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};
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&spi1 {
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status = "okay";
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num-cs = <4>;
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is-decoded-cs = <0>;
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flash@0 {
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compatible = "sst25wf080";
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reg = <1>;
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spi-max-frequency = <1000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@test {
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label = "spi-flash";
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reg = <0x0 0x100000>;
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};
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};
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};
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&can0 {
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status = "okay";
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};
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&gem0 {
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status = "okay";
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy>;
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ethernet_phy: ethernet-phy@7 {
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reg = <7>;
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};
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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m24c02_eeprom@52 {
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compatible = "at,24c02";
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reg = <0x52>;
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};
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};
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&sdhci0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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dr_mode = "host";
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usb-phy = <&usb_phy0>;
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};
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