mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 17:08:52 +09:00
255 lines
5.4 KiB
C
255 lines
5.4 KiB
C
/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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*
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* Dave Liu <daveliu@freescale.com>
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* based on source code of Shlomi Gridish
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "common.h"
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#include "asm/errno.h"
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#include "asm/io.h"
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#include "asm/immap_qe.h"
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#include "qe.h"
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#if defined(CONFIG_QE)
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qe_map_t *qe_immr = NULL;
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static qe_snum_t snums[QE_NUM_OF_SNUM];
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void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
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{
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u32 cecr;
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if (cmd == QE_RESET) {
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out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG));
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} else {
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out_be32(&qe_immr->cp.cecdr, cmd_data);
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out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG |
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((u32) mcn<<QE_CR_PROTOCOL_SHIFT) | cmd));
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}
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/* Wait for the QE_CR_FLG to clear */
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do {
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cecr = in_be32(&qe_immr->cp.cecr);
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} while (cecr & QE_CR_FLG);
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return;
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}
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uint qe_muram_alloc(uint size, uint align)
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{
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DECLARE_GLOBAL_DATA_PTR;
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uint retloc;
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uint align_mask, off;
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uint savebase;
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align_mask = align - 1;
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savebase = gd->mp_alloc_base;
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if ((off = (gd->mp_alloc_base & align_mask)) != 0)
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gd->mp_alloc_base += (align - off);
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if ((off = size & align_mask) != 0)
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size += (align - off);
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if ((gd->mp_alloc_base + size) >= gd->mp_alloc_top) {
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gd->mp_alloc_base = savebase;
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printf("%s: ran out of ram.\n", __FUNCTION__);
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}
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retloc = gd->mp_alloc_base;
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gd->mp_alloc_base += size;
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memset((void *)&qe_immr->muram[retloc], 0, size);
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__asm__ __volatile__("sync");
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return retloc;
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}
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void *qe_muram_addr(uint offset)
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{
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return (void *)&qe_immr->muram[offset];
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}
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static void qe_sdma_init(void)
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{
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volatile sdma_t *p;
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uint sdma_buffer_base;
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p = (volatile sdma_t *)&qe_immr->sdma;
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/* All of DMA transaction in bus 1 */
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out_be32(&p->sdaqr, 0);
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out_be32(&p->sdaqmr, 0);
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/* Allocate 2KB temporary buffer for sdma */
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sdma_buffer_base = qe_muram_alloc(2048, 64);
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out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK);
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/* Clear sdma status */
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out_be32(&p->sdsr, 0x03000000);
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/* Enable global mode on bus 1, and 2KB buffer size */
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out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT));
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}
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static u8 thread_snum[QE_NUM_OF_SNUM] = {
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0x04, 0x05, 0x0c, 0x0d,
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0x14, 0x15, 0x1c, 0x1d,
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0x24, 0x25, 0x2c, 0x2d,
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0x34, 0x35, 0x88, 0x89,
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0x98, 0x99, 0xa8, 0xa9,
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0xb8, 0xb9, 0xc8, 0xc9,
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0xd8, 0xd9, 0xe8, 0xe9
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};
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static void qe_snums_init(void)
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{
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int i;
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for (i = 0; i < QE_NUM_OF_SNUM; i++) {
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snums[i].state = QE_SNUM_STATE_FREE;
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snums[i].num = thread_snum[i];
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}
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}
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int qe_get_snum(void)
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{
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int snum = -EBUSY;
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int i;
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for (i = 0; i < QE_NUM_OF_SNUM; i++) {
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if (snums[i].state == QE_SNUM_STATE_FREE) {
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snums[i].state = QE_SNUM_STATE_USED;
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snum = snums[i].num;
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break;
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}
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}
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return snum;
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}
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void qe_put_snum(u8 snum)
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{
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int i;
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for (i = 0; i < QE_NUM_OF_SNUM; i++) {
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if (snums[i].num == snum) {
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snums[i].state = QE_SNUM_STATE_FREE;
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break;
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}
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}
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}
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void qe_init(uint qe_base)
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{
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DECLARE_GLOBAL_DATA_PTR;
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/* Init the QE IMMR base */
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qe_immr = (qe_map_t *)qe_base;
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gd->mp_alloc_base = QE_DATAONLY_BASE;
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gd->mp_alloc_top = gd->mp_alloc_base + QE_DATAONLY_SIZE;
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qe_sdma_init();
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qe_snums_init();
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}
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void qe_reset(void)
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{
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qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
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(u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
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}
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void qe_assign_page(uint snum, uint para_ram_base)
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{
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u32 cecr;
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out_be32(&qe_immr->cp.cecdr, para_ram_base);
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out_be32(&qe_immr->cp.cecr, ((u32) snum<<QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
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| QE_CR_FLG | QE_ASSIGN_PAGE);
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/* Wait for the QE_CR_FLG to clear */
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do {
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cecr = in_be32(&qe_immr->cp.cecr);
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} while (cecr & QE_CR_FLG );
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return;
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}
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/*
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* brg: 0~15 as BRG1~BRG16
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rate: baud rate
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* BRG input clock comes from the BRGCLK (internal clock generated from
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the QE clock, it is one-half of the QE clock), If need the clock source
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from CLKn pin, we have te change the function.
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*/
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#define BRG_CLK (gd->brg_clk)
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int qe_set_brg(uint brg, uint rate)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile uint *bp;
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u32 divisor;
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int div16 = 0;
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if (brg >= QE_NUM_OF_BRGS)
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return -EINVAL;
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bp = (uint *)&qe_immr->brg.brgc1;
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bp += brg;
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divisor = (BRG_CLK / rate);
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if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
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div16 = 1;
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divisor /= 16;
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}
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*bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
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__asm__ __volatile__("sync");
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if (div16) {
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*bp |= QE_BRGC_DIV16;
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__asm__ __volatile__("sync");
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}
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return 0;
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}
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/* Set ethernet MII clock master
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*/
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int qe_set_mii_clk_src(int ucc_num)
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{
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u32 cmxgcr;
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/* check if the UCC number is in range. */
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if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
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printf("%s: ucc num not in ranges\n", __FUNCTION__);
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return -EINVAL;
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}
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cmxgcr = in_be32(&qe_immr->qmx.cmxgcr);
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cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK;
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cmxgcr |= (ucc_num <<QE_CMXGCR_MII_ENET_MNG_SHIFT);
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out_be32(&qe_immr->qmx.cmxgcr, cmxgcr);
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return 0;
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}
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#endif /* CONFIG_QE */
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