395 lines
11 KiB
C
395 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Octeon family DWC3 specific glue layer
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*
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* Copyright (C) 2020 Stefan Roese <sr@denx.de>
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*
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* The low-level init code is based on the Linux driver octeon-usb.c by
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* David Daney <david.daney@cavium.com>, which is:
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* Copyright (C) 2010-2017 Cavium Networks
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*/
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#include <dm.h>
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#include <errno.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <dm/lists.h>
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#include <dm/of_access.h>
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/usb/dwc3.h>
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#include <linux/usb/otg.h>
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#include <mach/octeon-model.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define CVMX_GPIO_BIT_CFGX(i) (0x0001070000000900ull + ((i) * 8))
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#define CVMX_GPIO_XBIT_CFGX(i) (0x0001070000000900ull + \
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((i) & 31) * 8 - 8 * 16)
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#define GPIO_BIT_CFG_TX_OE BIT_ULL(0)
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#define GPIO_BIT_CFG_OUTPUT_SEL GENMASK_ULL(20, 16)
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#define UCTL_CTL_UCTL_RST BIT_ULL(0)
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#define UCTL_CTL_UAHC_RST BIT_ULL(1)
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#define UCTL_CTL_UPHY_RST BIT_ULL(2)
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#define UCTL_CTL_DRD_MODE BIT_ULL(3)
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#define UCTL_CTL_SCLK_EN BIT_ULL(4)
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#define UCTL_CTL_HS_POWER_EN BIT_ULL(12)
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#define UCTL_CTL_SS_POWER_EN BIT_ULL(14)
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#define UCTL_CTL_H_CLKDIV_SEL GENMASK_ULL(26, 24)
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#define UCTL_CTL_H_CLKDIV_RST BIT_ULL(28)
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#define UCTL_CTL_H_CLK_EN BIT_ULL(30)
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#define UCTL_CTL_REF_CLK_FSEL GENMASK_ULL(37, 32)
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#define UCTL_CTL_REF_CLK_DIV2 BIT_ULL(38)
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#define UCTL_CTL_REF_SSP_EN BIT_ULL(39)
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#define UCTL_CTL_MPLL_MULTIPLIER GENMASK_ULL(46, 40)
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#define UCTL_CTL_SSC_EN BIT_ULL(59)
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#define UCTL_CTL_REF_CLK_SEL GENMASK_ULL(61, 60)
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#define UCTL_HOST_CFG 0xe0
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#define UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN BIT_ULL(24)
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#define UCTL_HOST_CFG_PPC_EN BIT_ULL(25)
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#define UCTL_SHIM_CFG 0xe8
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#define UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK_ULL(1, 0)
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#define UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK_ULL(9, 8)
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#define OCTEON_H_CLKDIV_SEL 8
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#define OCTEON_MIN_H_CLK_RATE 150000000
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#define OCTEON_MAX_H_CLK_RATE 300000000
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#define CLOCK_50MHZ 50000000
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#define CLOCK_100MHZ 100000000
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#define CLOCK_125MHZ 125000000
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static u8 clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
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static int dwc3_octeon_config_power(struct udevice *dev, void __iomem *base)
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{
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u64 uctl_host_cfg;
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u64 gpio_bit;
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u32 gpio_pwr[3];
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int gpio, len, power_active_low;
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const struct device_node *node = dev_np(dev);
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int index = ((u64)base >> 24) & 1;
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void __iomem *gpio_bit_cfg;
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if (of_find_property(node, "power", &len)) {
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if (len == 12) {
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dev_read_u32_array(dev, "power", gpio_pwr, 3);
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power_active_low = gpio_pwr[2] & 0x01;
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gpio = gpio_pwr[1];
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} else if (len == 8) {
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dev_read_u32_array(dev, "power", gpio_pwr, 2);
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power_active_low = 0;
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gpio = gpio_pwr[1];
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} else {
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printf("dwc3 controller clock init failure\n");
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return -EINVAL;
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}
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gpio_bit_cfg = ioremap(CVMX_GPIO_BIT_CFGX(gpio), 0);
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if ((OCTEON_IS_MODEL(OCTEON_CN73XX) ||
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OCTEON_IS_MODEL(OCTEON_CNF75XX)) && gpio <= 31) {
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gpio_bit = ioread64(gpio_bit_cfg);
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gpio_bit |= GPIO_BIT_CFG_TX_OE;
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gpio_bit &= ~GPIO_BIT_CFG_OUTPUT_SEL;
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gpio_bit |= FIELD_PREP(GPIO_BIT_CFG_OUTPUT_SEL,
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index == 0 ? 0x14 : 0x15);
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iowrite64(gpio_bit, gpio_bit_cfg);
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} else if (gpio <= 15) {
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gpio_bit = ioread64(gpio_bit_cfg);
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gpio_bit |= GPIO_BIT_CFG_TX_OE;
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gpio_bit &= ~GPIO_BIT_CFG_OUTPUT_SEL;
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gpio_bit |= FIELD_PREP(GPIO_BIT_CFG_OUTPUT_SEL,
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index == 0 ? 0x14 : 0x19);
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iowrite64(gpio_bit, gpio_bit_cfg);
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} else {
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gpio_bit_cfg = ioremap(CVMX_GPIO_XBIT_CFGX(gpio), 0);
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gpio_bit = ioread64(gpio_bit_cfg);
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gpio_bit |= GPIO_BIT_CFG_TX_OE;
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gpio_bit &= ~GPIO_BIT_CFG_OUTPUT_SEL;
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gpio_bit |= FIELD_PREP(GPIO_BIT_CFG_OUTPUT_SEL,
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index == 0 ? 0x14 : 0x19);
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iowrite64(gpio_bit, gpio_bit_cfg);
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}
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/* Enable XHCI power control and set if active high or low. */
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uctl_host_cfg = ioread64(base + UCTL_HOST_CFG);
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uctl_host_cfg |= UCTL_HOST_CFG_PPC_EN;
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if (power_active_low)
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uctl_host_cfg &= ~UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN;
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else
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uctl_host_cfg |= UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN;
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iowrite64(uctl_host_cfg, base + UCTL_HOST_CFG);
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/* Wait for power to stabilize */
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mdelay(10);
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} else {
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/* Disable XHCI power control and set if active high. */
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uctl_host_cfg = ioread64(base + UCTL_HOST_CFG);
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uctl_host_cfg &= ~UCTL_HOST_CFG_PPC_EN;
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uctl_host_cfg &= ~UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN;
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iowrite64(uctl_host_cfg, base + UCTL_HOST_CFG);
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dev_warn(dev, "dwc3 controller clock init failure.\n");
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}
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return 0;
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}
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static int dwc3_octeon_clocks_start(struct udevice *dev, void __iomem *base)
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{
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u64 uctl_ctl;
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int ref_clk_sel = 2;
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u64 div;
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u32 clock_rate;
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int mpll_mul;
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int i;
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u64 h_clk_rate;
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void __iomem *uctl_ctl_reg = base;
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const char *ss_clock_type;
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const char *hs_clock_type;
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i = dev_read_u32(dev, "refclk-frequency", &clock_rate);
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if (i) {
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printf("No UCTL \"refclk-frequency\"\n");
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return -EINVAL;
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}
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ss_clock_type = dev_read_string(dev, "refclk-type-ss");
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if (!ss_clock_type) {
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printf("No UCTL \"refclk-type-ss\"\n");
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return -EINVAL;
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}
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hs_clock_type = dev_read_string(dev, "refclk-type-hs");
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if (!hs_clock_type) {
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printf("No UCTL \"refclk-type-hs\"\n");
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return -EINVAL;
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}
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if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) {
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if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) {
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ref_clk_sel = 0;
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} else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) {
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ref_clk_sel = 2;
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} else {
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printf("Invalid HS clock type %s, using pll_ref_clk\n",
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hs_clock_type);
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}
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} else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) {
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if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) {
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ref_clk_sel = 1;
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} else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) {
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ref_clk_sel = 3;
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} else {
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printf("Invalid HS clock type %s, using pll_ref_clk\n",
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hs_clock_type);
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ref_clk_sel = 3;
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}
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} else {
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printf("Invalid SS clock type %s, using dlmc_ref_clk0\n",
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ss_clock_type);
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}
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if ((ref_clk_sel == 0 || ref_clk_sel == 1) &&
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clock_rate != CLOCK_100MHZ)
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printf("Invalid UCTL clock rate of %u\n", clock_rate);
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/*
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* Step 1: Wait for all voltages to be stable...that surely
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* happened before this driver is started. SKIP
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*/
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/* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */
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/* Step 3: Assert all resets. */
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uctl_ctl = ioread64(uctl_ctl_reg);
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uctl_ctl |= UCTL_CTL_UCTL_RST | UCTL_CTL_UAHC_RST | UCTL_CTL_UPHY_RST;
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iowrite64(uctl_ctl, uctl_ctl_reg);
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/* Step 4a: Reset the clock dividers. */
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uctl_ctl = ioread64(uctl_ctl_reg);
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uctl_ctl |= UCTL_CTL_H_CLKDIV_RST;
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iowrite64(uctl_ctl, uctl_ctl_reg);
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/* Step 4b: Select controller clock frequency. */
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for (div = ARRAY_SIZE(clk_div) - 1; div >= 0; div--) {
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h_clk_rate = gd->bus_clk / clk_div[div];
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if (h_clk_rate <= OCTEON_MAX_H_CLK_RATE &&
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h_clk_rate >= OCTEON_MIN_H_CLK_RATE)
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break;
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}
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uctl_ctl = ioread64(uctl_ctl_reg);
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uctl_ctl &= ~UCTL_CTL_H_CLKDIV_SEL;
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uctl_ctl |= FIELD_PREP(UCTL_CTL_H_CLKDIV_SEL, div);
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uctl_ctl |= UCTL_CTL_H_CLK_EN;
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iowrite64(uctl_ctl, uctl_ctl_reg);
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uctl_ctl = ioread64(uctl_ctl_reg);
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if (div != FIELD_GET(UCTL_CTL_H_CLKDIV_SEL, uctl_ctl) ||
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!(uctl_ctl & UCTL_CTL_H_CLK_EN)) {
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printf("dwc3 controller clock init failure\n");
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return -EINVAL;
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}
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/* Step 4c: Deassert the controller clock divider reset. */
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uctl_ctl = ioread64(uctl_ctl_reg);
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uctl_ctl &= ~UCTL_CTL_H_CLKDIV_RST;
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iowrite64(uctl_ctl, uctl_ctl_reg);
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/* Step 5a: Reference clock configuration. */
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uctl_ctl = ioread64(uctl_ctl_reg);
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uctl_ctl &= ~UCTL_CTL_REF_CLK_SEL;
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uctl_ctl |= FIELD_PREP(UCTL_CTL_REF_CLK_SEL, ref_clk_sel);
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uctl_ctl &= ~UCTL_CTL_REF_CLK_FSEL;
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uctl_ctl |= FIELD_PREP(UCTL_CTL_REF_CLK_FSEL, 0x07);
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uctl_ctl &= ~UCTL_CTL_REF_CLK_DIV2;
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switch (clock_rate) {
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default:
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printf("Invalid ref_clk %u, using %u instead\n", CLOCK_100MHZ,
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clock_rate);
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fallthrough;
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case CLOCK_100MHZ:
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mpll_mul = 0x19;
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if (ref_clk_sel < 2) {
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uctl_ctl &= ~UCTL_CTL_REF_CLK_FSEL;
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uctl_ctl |= FIELD_PREP(UCTL_CTL_REF_CLK_FSEL, 0x27);
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}
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break;
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case CLOCK_50MHZ:
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mpll_mul = 0x32;
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break;
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case CLOCK_125MHZ:
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mpll_mul = 0x28;
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break;
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}
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uctl_ctl &= ~UCTL_CTL_MPLL_MULTIPLIER;
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uctl_ctl |= FIELD_PREP(UCTL_CTL_MPLL_MULTIPLIER, mpll_mul);
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/* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */
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uctl_ctl |= UCTL_CTL_SSC_EN;
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/* Step 5c: Enable SuperSpeed. */
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uctl_ctl |= UCTL_CTL_REF_SSP_EN;
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/* Step 5d: Configure PHYs. SKIP */
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/* Step 6a & 6b: Power up PHYs. */
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uctl_ctl |= UCTL_CTL_HS_POWER_EN;
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uctl_ctl |= UCTL_CTL_SS_POWER_EN;
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iowrite64(uctl_ctl, uctl_ctl_reg);
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/* Step 7: Wait 10 controller-clock cycles to take effect. */
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udelay(10);
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/* Step 8a: Deassert UCTL reset signal. */
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uctl_ctl = ioread64(uctl_ctl_reg);
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uctl_ctl &= ~UCTL_CTL_UCTL_RST;
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iowrite64(uctl_ctl, uctl_ctl_reg);
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/* Step 8b: Wait 10 controller-clock cycles. */
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udelay(10);
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/* Step 8c: Setup power-power control. */
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if (dwc3_octeon_config_power(dev, base)) {
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printf("Error configuring power\n");
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return -EINVAL;
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}
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/* Step 8d: Deassert UAHC reset signal. */
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uctl_ctl = ioread64(uctl_ctl_reg);
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uctl_ctl &= ~UCTL_CTL_UAHC_RST;
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iowrite64(uctl_ctl, uctl_ctl_reg);
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/* Step 8e: Wait 10 controller-clock cycles. */
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udelay(10);
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/* Step 9: Enable conditional coprocessor clock of UCTL. */
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uctl_ctl = ioread64(uctl_ctl_reg);
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uctl_ctl |= UCTL_CTL_SCLK_EN;
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iowrite64(uctl_ctl, uctl_ctl_reg);
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/* Step 10: Set for host mode only. */
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uctl_ctl = ioread64(uctl_ctl_reg);
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uctl_ctl &= ~UCTL_CTL_DRD_MODE;
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iowrite64(uctl_ctl, uctl_ctl_reg);
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return 0;
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}
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static void dwc3_octeon_set_endian_mode(void __iomem *base)
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{
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u64 shim_cfg;
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shim_cfg = ioread64(base + UCTL_SHIM_CFG);
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shim_cfg &= ~UCTL_SHIM_CFG_CSR_ENDIAN_MODE;
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shim_cfg |= FIELD_PREP(UCTL_SHIM_CFG_CSR_ENDIAN_MODE, 1);
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shim_cfg &= ~UCTL_SHIM_CFG_DMA_ENDIAN_MODE;
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shim_cfg |= FIELD_PREP(UCTL_SHIM_CFG_DMA_ENDIAN_MODE, 1);
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iowrite64(shim_cfg, base + UCTL_SHIM_CFG);
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}
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static void dwc3_octeon_phy_reset(void __iomem *base)
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{
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u64 uctl_ctl;
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uctl_ctl = ioread64(base);
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uctl_ctl &= ~UCTL_CTL_UPHY_RST;
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iowrite64(uctl_ctl, base);
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}
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static int octeon_dwc3_glue_probe(struct udevice *dev)
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{
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void __iomem *base;
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base = dev_remap_addr(dev);
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if (IS_ERR(base))
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return PTR_ERR(base);
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dwc3_octeon_clocks_start(dev, base);
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dwc3_octeon_set_endian_mode(base);
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dwc3_octeon_phy_reset(base);
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return 0;
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}
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static int octeon_dwc3_glue_bind(struct udevice *dev)
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{
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ofnode node, dwc3_node;
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/* Find snps,dwc3 node from subnode */
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dwc3_node = ofnode_null();
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ofnode_for_each_subnode(node, dev_ofnode(dev)) {
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if (ofnode_device_is_compatible(node, "snps,dwc3"))
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dwc3_node = node;
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}
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if (!ofnode_valid(dwc3_node)) {
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printf("Can't find dwc3 subnode for %s\n", dev->name);
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return -ENODEV;
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}
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return dm_scan_fdt_dev(dev);
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}
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static const struct udevice_id octeon_dwc3_glue_ids[] = {
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{ .compatible = "cavium,octeon-7130-usb-uctl" },
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{ }
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};
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U_BOOT_DRIVER(dwc3_octeon_glue) = {
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.name = "dwc3_octeon_glue",
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.id = UCLASS_NOP,
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.of_match = octeon_dwc3_glue_ids,
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.probe = octeon_dwc3_glue_probe,
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.bind = octeon_dwc3_glue_bind,
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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