465 lines
10 KiB
C
465 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Generic DWC3 Glue layer
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*
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* Copyright (C) 2016 - 2018 Xilinx, Inc.
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*
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* Based on dwc3-omap.c.
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <log.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dwc3-uboot.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <malloc.h>
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#include <usb.h>
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#include "core.h"
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#include "gadget.h"
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#include <reset.h>
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#include <clk.h>
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#include <usb/xhci.h>
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struct dwc3_glue_data {
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struct clk_bulk clks;
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struct reset_ctl_bulk resets;
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fdt_addr_t regs;
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};
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struct dwc3_generic_plat {
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fdt_addr_t base;
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u32 maximum_speed;
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enum usb_dr_mode dr_mode;
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};
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struct dwc3_generic_priv {
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void *base;
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struct dwc3 dwc3;
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struct phy_bulk phys;
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};
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struct dwc3_generic_host_priv {
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struct xhci_ctrl xhci_ctrl;
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struct dwc3_generic_priv gen_priv;
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};
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static int dwc3_generic_probe(struct udevice *dev,
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struct dwc3_generic_priv *priv)
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{
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int rc;
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struct dwc3_generic_plat *plat = dev_get_plat(dev);
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struct dwc3 *dwc3 = &priv->dwc3;
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struct dwc3_glue_data *glue = dev_get_plat(dev->parent);
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dwc3->dev = dev;
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dwc3->maximum_speed = plat->maximum_speed;
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dwc3->dr_mode = plat->dr_mode;
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#if CONFIG_IS_ENABLED(OF_CONTROL)
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dwc3_of_parse(dwc3);
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#endif
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/*
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* It must hold whole USB3.0 OTG controller in resetting to hold pipe
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* power state in P2 before initializing TypeC PHY on RK3399 platform.
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*/
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if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) {
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reset_assert_bulk(&glue->resets);
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udelay(1);
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}
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rc = dwc3_setup_phy(dev, &priv->phys);
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if (rc && rc != -ENOTSUPP)
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return rc;
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if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3"))
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reset_deassert_bulk(&glue->resets);
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priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
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dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
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rc = dwc3_init(dwc3);
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if (rc) {
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unmap_physmem(priv->base, MAP_NOCACHE);
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return rc;
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}
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return 0;
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}
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static int dwc3_generic_remove(struct udevice *dev,
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struct dwc3_generic_priv *priv)
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{
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struct dwc3 *dwc3 = &priv->dwc3;
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dwc3_remove(dwc3);
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dwc3_shutdown_phy(dev, &priv->phys);
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unmap_physmem(dwc3->regs, MAP_NOCACHE);
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return 0;
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}
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static int dwc3_generic_of_to_plat(struct udevice *dev)
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{
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struct dwc3_generic_plat *plat = dev_get_plat(dev);
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ofnode node = dev_ofnode(dev);
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plat->base = dev_read_addr(dev);
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plat->maximum_speed = usb_get_maximum_speed(node);
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if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
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pr_info("No USB maximum speed specified. Using super speed\n");
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plat->maximum_speed = USB_SPEED_SUPER;
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}
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plat->dr_mode = usb_get_dr_mode(node);
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if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
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pr_err("Invalid usb mode setup\n");
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return -ENODEV;
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}
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return 0;
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}
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#if CONFIG_IS_ENABLED(DM_USB_GADGET)
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int dm_usb_gadget_handle_interrupts(struct udevice *dev)
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{
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struct dwc3_generic_priv *priv = dev_get_priv(dev);
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struct dwc3 *dwc3 = &priv->dwc3;
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dwc3_gadget_uboot_handle_interrupt(dwc3);
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return 0;
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}
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static int dwc3_generic_peripheral_probe(struct udevice *dev)
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{
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struct dwc3_generic_priv *priv = dev_get_priv(dev);
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return dwc3_generic_probe(dev, priv);
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}
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static int dwc3_generic_peripheral_remove(struct udevice *dev)
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{
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struct dwc3_generic_priv *priv = dev_get_priv(dev);
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return dwc3_generic_remove(dev, priv);
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}
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U_BOOT_DRIVER(dwc3_generic_peripheral) = {
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.name = "dwc3-generic-peripheral",
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.id = UCLASS_USB_GADGET_GENERIC,
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.of_to_plat = dwc3_generic_of_to_plat,
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.probe = dwc3_generic_peripheral_probe,
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.remove = dwc3_generic_peripheral_remove,
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.priv_auto = sizeof(struct dwc3_generic_priv),
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.plat_auto = sizeof(struct dwc3_generic_plat),
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};
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#endif
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#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
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static int dwc3_generic_host_probe(struct udevice *dev)
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{
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struct xhci_hcor *hcor;
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struct xhci_hccr *hccr;
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struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
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int rc;
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rc = dwc3_generic_probe(dev, &priv->gen_priv);
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if (rc)
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return rc;
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hccr = (struct xhci_hccr *)priv->gen_priv.base;
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hcor = (struct xhci_hcor *)(priv->gen_priv.base +
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HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
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return xhci_register(dev, hccr, hcor);
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}
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static int dwc3_generic_host_remove(struct udevice *dev)
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{
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struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
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int rc;
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rc = xhci_deregister(dev);
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if (rc)
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return rc;
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return dwc3_generic_remove(dev, &priv->gen_priv);
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}
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U_BOOT_DRIVER(dwc3_generic_host) = {
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.name = "dwc3-generic-host",
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.id = UCLASS_USB,
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.of_to_plat = dwc3_generic_of_to_plat,
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.probe = dwc3_generic_host_probe,
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.remove = dwc3_generic_host_remove,
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.priv_auto = sizeof(struct dwc3_generic_host_priv),
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.plat_auto = sizeof(struct dwc3_generic_plat),
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.ops = &xhci_usb_ops,
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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#endif
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struct dwc3_glue_ops {
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void (*select_dr_mode)(struct udevice *dev, int index,
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enum usb_dr_mode mode);
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};
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void dwc3_ti_select_dr_mode(struct udevice *dev, int index,
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enum usb_dr_mode mode)
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{
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#define USBOTGSS_UTMI_OTG_STATUS 0x0084
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#define USBOTGSS_UTMI_OTG_OFFSET 0x0480
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/* UTMI_OTG_STATUS REGISTER */
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#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE BIT(31)
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#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT BIT(9)
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#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE BIT(8)
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#define USBOTGSS_UTMI_OTG_STATUS_IDDIG BIT(4)
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#define USBOTGSS_UTMI_OTG_STATUS_SESSEND BIT(3)
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#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID BIT(2)
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#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID BIT(1)
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enum dwc3_omap_utmi_mode {
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DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
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DWC3_OMAP_UTMI_MODE_HW,
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DWC3_OMAP_UTMI_MODE_SW,
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};
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u32 use_id_pin;
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u32 host_mode;
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u32 reg;
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u32 utmi_mode;
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u32 utmi_status_offset = USBOTGSS_UTMI_OTG_STATUS;
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struct dwc3_glue_data *glue = dev_get_plat(dev);
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void *base = map_physmem(glue->regs, 0x10000, MAP_NOCACHE);
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if (device_is_compatible(dev, "ti,am437x-dwc3"))
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utmi_status_offset += USBOTGSS_UTMI_OTG_OFFSET;
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utmi_mode = dev_read_u32_default(dev, "utmi-mode",
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DWC3_OMAP_UTMI_MODE_UNKNOWN);
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if (utmi_mode != DWC3_OMAP_UTMI_MODE_HW) {
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debug("%s: OTG is not supported. defaulting to PERIPHERAL\n",
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dev->name);
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mode = USB_DR_MODE_PERIPHERAL;
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}
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switch (mode) {
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case USB_DR_MODE_PERIPHERAL:
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use_id_pin = 0;
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host_mode = 0;
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break;
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case USB_DR_MODE_HOST:
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use_id_pin = 0;
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host_mode = 1;
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break;
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case USB_DR_MODE_OTG:
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default:
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use_id_pin = 1;
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host_mode = 0;
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break;
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}
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reg = readl(base + utmi_status_offset);
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reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SW_MODE);
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if (!use_id_pin)
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reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
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writel(reg, base + utmi_status_offset);
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reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSEND |
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USBOTGSS_UTMI_OTG_STATUS_VBUSVALID |
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USBOTGSS_UTMI_OTG_STATUS_IDDIG);
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reg |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID |
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USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
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if (!host_mode)
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reg |= USBOTGSS_UTMI_OTG_STATUS_IDDIG |
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USBOTGSS_UTMI_OTG_STATUS_VBUSVALID;
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writel(reg, base + utmi_status_offset);
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unmap_physmem(base, MAP_NOCACHE);
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}
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struct dwc3_glue_ops ti_ops = {
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.select_dr_mode = dwc3_ti_select_dr_mode,
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};
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static int dwc3_glue_bind(struct udevice *parent)
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{
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ofnode node;
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int ret;
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ofnode_for_each_subnode(node, dev_ofnode(parent)) {
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const char *name = ofnode_get_name(node);
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enum usb_dr_mode dr_mode;
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struct udevice *dev;
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const char *driver = NULL;
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debug("%s: subnode name: %s\n", __func__, name);
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dr_mode = usb_get_dr_mode(node);
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switch (dr_mode) {
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case USB_DR_MODE_PERIPHERAL:
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case USB_DR_MODE_OTG:
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#if CONFIG_IS_ENABLED(DM_USB_GADGET)
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debug("%s: dr_mode: OTG or Peripheral\n", __func__);
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driver = "dwc3-generic-peripheral";
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#endif
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break;
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#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
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case USB_DR_MODE_HOST:
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debug("%s: dr_mode: HOST\n", __func__);
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driver = "dwc3-generic-host";
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break;
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#endif
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default:
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debug("%s: unsupported dr_mode\n", __func__);
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return -ENODEV;
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};
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if (!driver)
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continue;
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ret = device_bind_driver_to_node(parent, driver, name,
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node, &dev);
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if (ret) {
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debug("%s: not able to bind usb device mode\n",
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__func__);
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return ret;
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}
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}
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return 0;
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}
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static int dwc3_glue_reset_init(struct udevice *dev,
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struct dwc3_glue_data *glue)
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{
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int ret;
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ret = reset_get_bulk(dev, &glue->resets);
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if (ret == -ENOTSUPP || ret == -ENOENT)
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return 0;
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else if (ret)
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return ret;
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ret = reset_deassert_bulk(&glue->resets);
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if (ret) {
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reset_release_bulk(&glue->resets);
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return ret;
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}
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return 0;
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}
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static int dwc3_glue_clk_init(struct udevice *dev,
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struct dwc3_glue_data *glue)
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{
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int ret;
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ret = clk_get_bulk(dev, &glue->clks);
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if (ret == -ENOSYS || ret == -ENOENT)
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return 0;
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if (ret)
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return ret;
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#if CONFIG_IS_ENABLED(CLK)
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ret = clk_enable_bulk(&glue->clks);
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if (ret) {
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clk_release_bulk(&glue->clks);
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return ret;
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}
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#endif
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return 0;
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}
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static int dwc3_glue_probe(struct udevice *dev)
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{
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struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(dev);
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struct dwc3_glue_data *glue = dev_get_plat(dev);
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struct udevice *child = NULL;
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int index = 0;
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int ret;
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glue->regs = dev_read_addr(dev);
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ret = dwc3_glue_clk_init(dev, glue);
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if (ret)
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return ret;
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ret = dwc3_glue_reset_init(dev, glue);
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if (ret)
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return ret;
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ret = device_find_first_child(dev, &child);
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if (ret)
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return ret;
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if (glue->resets.count == 0) {
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ret = dwc3_glue_reset_init(child, glue);
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if (ret)
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return ret;
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}
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while (child) {
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enum usb_dr_mode dr_mode;
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dr_mode = usb_get_dr_mode(dev_ofnode(child));
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device_find_next_child(&child);
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if (ops && ops->select_dr_mode)
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ops->select_dr_mode(dev, index, dr_mode);
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index++;
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}
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return 0;
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}
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static int dwc3_glue_remove(struct udevice *dev)
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{
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struct dwc3_glue_data *glue = dev_get_plat(dev);
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reset_release_bulk(&glue->resets);
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clk_release_bulk(&glue->clks);
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return 0;
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}
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static const struct udevice_id dwc3_glue_ids[] = {
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{ .compatible = "xlnx,zynqmp-dwc3" },
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{ .compatible = "xlnx,versal-dwc3" },
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{ .compatible = "ti,keystone-dwc3"},
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{ .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
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{ .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
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{ .compatible = "ti,am654-dwc3" },
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{ .compatible = "rockchip,rk3328-dwc3" },
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{ .compatible = "rockchip,rk3399-dwc3" },
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{ .compatible = "qcom,dwc3" },
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{ }
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};
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U_BOOT_DRIVER(dwc3_generic_wrapper) = {
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.name = "dwc3-generic-wrapper",
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.id = UCLASS_NOP,
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.of_match = dwc3_glue_ids,
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.bind = dwc3_glue_bind,
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.probe = dwc3_glue_probe,
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.remove = dwc3_glue_remove,
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.plat_auto = sizeof(struct dwc3_glue_data),
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};
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