mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 07:16:04 +09:00
edd9ad8194
Add a callback harts_early_init() to start.S to allow different riscv hart perform setup code for each hart as early as possible. Since all the harts enter the callback, they must be able to run the same setup. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
451 lines
9.5 KiB
ArmAsm
451 lines
9.5 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Startup Code for RISC-V Core
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*
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* Copyright (c) 2017 Microsemi Corporation.
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* Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
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*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <common.h>
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#include <elf.h>
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#include <asm/encoding.h>
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#include <generated/asm-offsets.h>
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#ifdef CONFIG_32BIT
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#define LREG lw
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#define SREG sw
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#define REGBYTES 4
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#define RELOC_TYPE R_RISCV_32
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#define SYM_INDEX 0x8
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#define SYM_SIZE 0x10
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#else
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#define LREG ld
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#define SREG sd
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#define REGBYTES 8
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#define RELOC_TYPE R_RISCV_64
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#define SYM_INDEX 0x20
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#define SYM_SIZE 0x18
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#endif
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.section .data
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secondary_harts_relocation_error:
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.ascii "Relocation of secondary harts has failed, error %d\n"
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.section .text
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.globl _start
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_start:
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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csrr a0, CSR_MHARTID
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#endif
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/*
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* Save hart id and dtb pointer. The thread pointer register is not
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* modified by C code. It is used by secondary_hart_loop.
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*/
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mv tp, a0
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mv s1, a1
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/*
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* Set the global data pointer to a known value in case we get a very
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* early trap. The global data pointer will be set its actual value only
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* after it has been initialized.
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*/
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mv gp, zero
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/*
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* Set the trap handler. This must happen after initializing gp because
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* the handler may use it.
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*/
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la t0, trap_entry
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csrw MODE_PREFIX(tvec), t0
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/*
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* Mask all interrupts. Interrupts are disabled globally (in m/sstatus)
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* for U-Boot, but we will need to read m/sip to determine if we get an
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* IPI
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*/
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csrw MODE_PREFIX(ie), zero
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#if CONFIG_IS_ENABLED(SMP)
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/* check if hart is within range */
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/* tp: hart id */
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li t0, CONFIG_NR_CPUS
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bge tp, t0, hart_out_of_bounds_loop
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/* set xSIE bit to receive IPIs */
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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li t0, MIE_MSIE
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#else
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li t0, SIE_SSIE
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#endif
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csrs MODE_PREFIX(ie), t0
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#endif
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/*
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* Set stackpointer in internal/ex RAM to call board_init_f
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*/
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call_board_init_f:
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li t0, -16
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
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li t1, CONFIG_SPL_STACK
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#else
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li t1, CONFIG_SYS_INIT_SP_ADDR
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#endif
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and sp, t1, t0 /* force 16 byte alignment */
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call_board_init_f_0:
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mv a0, sp
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jal board_init_f_alloc_reserve
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/*
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* Save global data pointer for later. We don't set it here because it
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* is not initialized yet.
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*/
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mv s0, a0
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/* setup stack */
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#if CONFIG_IS_ENABLED(SMP)
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/* tp: hart id */
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slli t0, tp, CONFIG_STACK_SIZE_SHIFT
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sub sp, a0, t0
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#else
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mv sp, a0
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#endif
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/* Configure proprietary settings and customized CSRs of harts */
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call_harts_early_init:
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jal harts_early_init
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#ifndef CONFIG_XIP
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/*
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* Pick hart to initialize global data and run U-Boot. The other harts
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* wait for initialization to complete.
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*/
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la t0, hart_lottery
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li t1, 1
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amoswap.w s2, t1, 0(t0)
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bnez s2, wait_for_gd_init
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#else
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/*
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* FIXME: gp is set before it is initialized. If an XIP U-Boot ever
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* encounters a pending IPI on boot it is liable to jump to whatever
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* memory happens to be in ipi_data.addr on boot. It may also run into
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* problems if it encounters an exception too early (because printf/puts
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* accesses gd).
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*/
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mv gp, s0
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bnez tp, secondary_hart_loop
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#endif
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#ifdef CONFIG_OF_PRIOR_STAGE
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la t0, prior_stage_fdt_address
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SREG s1, 0(t0)
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#endif
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jal board_init_f_init_reserve
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SREG s1, GD_FIRMWARE_FDT_ADDR(gp)
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/* save the boot hart id to global_data */
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SREG tp, GD_BOOT_HART(gp)
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#ifndef CONFIG_XIP
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la t0, available_harts_lock
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amoswap.w.rl zero, zero, 0(t0)
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wait_for_gd_init:
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la t0, available_harts_lock
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li t1, 1
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1: amoswap.w.aq t1, t1, 0(t0)
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bnez t1, 1b
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/*
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* Set the global data pointer only when gd_t has been initialized.
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* This was already set by arch_setup_gd on the boot hart, but all other
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* harts' global data pointers gets set here.
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*/
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mv gp, s0
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/* register available harts in the available_harts mask */
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li t1, 1
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sll t1, t1, tp
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LREG t2, GD_AVAILABLE_HARTS(gp)
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or t2, t2, t1
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SREG t2, GD_AVAILABLE_HARTS(gp)
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amoswap.w.rl zero, zero, 0(t0)
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/*
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* Continue on hart lottery winner, others branch to
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* secondary_hart_loop.
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*/
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bnez s2, secondary_hart_loop
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#endif
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/* Enable cache */
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jal icache_enable
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jal dcache_enable
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#ifdef CONFIG_DEBUG_UART
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jal debug_uart_init
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#endif
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mv a0, zero /* a0 <-- boot_flags = 0 */
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la t5, board_init_f
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jalr t5 /* jump to board_init_f() */
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#ifdef CONFIG_SPL_BUILD
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spl_clear_bss:
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la t0, __bss_start
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la t1, __bss_end
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beq t0, t1, spl_stack_gd_setup
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spl_clear_bss_loop:
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SREG zero, 0(t0)
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addi t0, t0, REGBYTES
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blt t0, t1, spl_clear_bss_loop
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spl_stack_gd_setup:
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jal spl_relocate_stack_gd
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/* skip setup if we did not relocate */
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beqz a0, spl_call_board_init_r
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mv s0, a0
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/* setup stack on main hart */
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#if CONFIG_IS_ENABLED(SMP)
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/* tp: hart id */
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slli t0, tp, CONFIG_STACK_SIZE_SHIFT
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sub sp, s0, t0
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#else
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mv sp, s0
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#endif
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#if CONFIG_IS_ENABLED(SMP)
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/* set new stack and global data pointer on secondary harts */
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spl_secondary_hart_stack_gd_setup:
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la a0, secondary_hart_relocate
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mv a1, s0
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mv a2, s0
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mv a3, zero
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jal smp_call_function
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/* hang if relocation of secondary harts has failed */
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beqz a0, 1f
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mv a1, a0
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la a0, secondary_harts_relocation_error
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jal printf
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jal hang
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#endif
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/* set new global data pointer on main hart */
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1: mv gp, s0
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spl_call_board_init_r:
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mv a0, zero
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mv a1, zero
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jal board_init_r
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#endif
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/*
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* void relocate_code(addr_sp, gd, addr_moni)
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*
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* This "function" does not return, instead it continues in RAM
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* after relocating the monitor code.
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*
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*/
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.globl relocate_code
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relocate_code:
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mv s2, a0 /* save addr_sp */
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mv s3, a1 /* save addr of gd */
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mv s4, a2 /* save addr of destination */
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/*
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*Set up the stack
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*/
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stack_setup:
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#if CONFIG_IS_ENABLED(SMP)
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/* tp: hart id */
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slli t0, tp, CONFIG_STACK_SIZE_SHIFT
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sub sp, s2, t0
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#else
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mv sp, s2
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#endif
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la t0, _start
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sub t6, s4, t0 /* t6 <- relocation offset */
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beq t0, s4, clear_bss /* skip relocation */
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mv t1, s4 /* t1 <- scratch for copy_loop */
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la t3, __bss_start
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sub t3, t3, t0 /* t3 <- __bss_start_ofs */
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add t2, t0, t3 /* t2 <- source end address */
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copy_loop:
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LREG t5, 0(t0)
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addi t0, t0, REGBYTES
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SREG t5, 0(t1)
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addi t1, t1, REGBYTES
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blt t0, t2, copy_loop
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/*
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* Update dynamic relocations after board_init_f
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*/
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fix_rela_dyn:
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la t1, __rel_dyn_start
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la t2, __rel_dyn_end
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beq t1, t2, clear_bss
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add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */
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add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */
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/*
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* skip first reserved entry: address, type, addend
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*/
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j 10f
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6:
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LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
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li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
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bne t5, t3, 8f /* skip non-RISCV_RELOC entries */
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LREG t3, -(REGBYTES*3)(t1)
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LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */
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add t5, t5, t6 /* t5 <-- location to fix up in RAM */
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add t3, t3, t6 /* t3 <-- location to fix up in RAM */
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SREG t5, 0(t3)
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j 10f
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8:
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la t4, __dyn_sym_start
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add t4, t4, t6
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9:
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LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
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srli t0, t5, SYM_INDEX /* t0 <--- sym table index */
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andi t5, t5, 0xFF /* t5 <--- relocation type */
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li t3, RELOC_TYPE
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bne t5, t3, 10f /* skip non-addned entries */
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LREG t3, -(REGBYTES*3)(t1)
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li t5, SYM_SIZE
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mul t0, t0, t5
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add s5, t4, t0
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LREG t0, -(REGBYTES)(t1) /* t0 <-- addend */
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LREG t5, REGBYTES(s5)
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add t5, t5, t0
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add t5, t5, t6 /* t5 <-- location to fix up in RAM */
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add t3, t3, t6 /* t3 <-- location to fix up in RAM */
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SREG t5, 0(t3)
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10:
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addi t1, t1, (REGBYTES*3)
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ble t1, t2, 6b
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/*
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* trap update
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*/
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la t0, trap_entry
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add t0, t0, t6
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csrw MODE_PREFIX(tvec), t0
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clear_bss:
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la t0, __bss_start /* t0 <- rel __bss_start in FLASH */
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add t0, t0, t6 /* t0 <- rel __bss_start in RAM */
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la t1, __bss_end /* t1 <- rel __bss_end in FLASH */
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add t1, t1, t6 /* t1 <- rel __bss_end in RAM */
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beq t0, t1, relocate_secondary_harts
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clbss_l:
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SREG zero, 0(t0) /* clear loop... */
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addi t0, t0, REGBYTES
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blt t0, t1, clbss_l
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relocate_secondary_harts:
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#if CONFIG_IS_ENABLED(SMP)
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/* send relocation IPI */
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la t0, secondary_hart_relocate
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add a0, t0, t6
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/* store relocation offset */
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mv s5, t6
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mv a1, s2
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mv a2, s3
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mv a3, zero
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jal smp_call_function
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/* hang if relocation of secondary harts has failed */
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beqz a0, 1f
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mv a1, a0
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la a0, secondary_harts_relocation_error
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jal printf
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jal hang
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/* restore relocation offset */
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1: mv t6, s5
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#endif
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/*
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* We are done. Do not return, instead branch to second part of board
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* initialization, now running from RAM.
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*/
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call_board_init_r:
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jal invalidate_icache_all
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jal flush_dcache_all
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la t0, board_init_r /* offset of board_init_r() */
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add t4, t0, t6 /* real address of board_init_r() */
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/*
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* setup parameters for board_init_r
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*/
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mv a0, s3 /* gd_t */
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mv a1, s4 /* dest_addr */
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/*
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* jump to it ...
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*/
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jr t4 /* jump to board_init_r() */
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#if CONFIG_IS_ENABLED(SMP)
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hart_out_of_bounds_loop:
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/* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */
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wfi
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j hart_out_of_bounds_loop
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/* SMP relocation entry */
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secondary_hart_relocate:
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/* a1: new sp */
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/* a2: new gd */
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/* tp: hart id */
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/* setup stack */
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slli t0, tp, CONFIG_STACK_SIZE_SHIFT
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sub sp, a1, t0
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/* update global data pointer */
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mv gp, a2
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#endif
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/*
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* Interrupts are disabled globally, but they can still be read from m/sip. The
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* wfi function will wake us up if we get an IPI, even if we do not trap.
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*/
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secondary_hart_loop:
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wfi
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#if CONFIG_IS_ENABLED(SMP)
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csrr t0, MODE_PREFIX(ip)
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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andi t0, t0, MIE_MSIE
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#else
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andi t0, t0, SIE_SSIE
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#endif
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beqz t0, secondary_hart_loop
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mv a0, tp
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jal handle_ipi
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#endif
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j secondary_hart_loop
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