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ab1b955211
For files like the drivers/serial/serial.c, it must include the platform file, as the CONFIG_SYS_NS16550_COM1 must reference to the definition in the platform definition files. Include the platform definition file in the config file, so that it would decouple the dependence for the driver files. Updated cpu.h to remove build errors for gplugd board (by prafulla) Signed-off-by: Lei Wen <leiwen@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
68 lines
2.3 KiB
C
68 lines
2.3 KiB
C
/*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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* Contributor: Mahavir Jain <mjain@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#ifndef _ASM_ARCH_ARMADA100_H
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#define _ASM_ARCH_ARMADA100_H
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#if defined (CONFIG_ARMADA100)
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/* Common APB clock register bit definitions */
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#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
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#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
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#define APBC_RST (1<<2) /* Reset Generation */
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/* Functional Clock Selection Mask */
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#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
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/* Fast Ethernet Controller Clock register definition */
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#define FE_CLK_RST 0x1
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#define FE_CLK_ENA 0x8
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/* SSP2 Clock Control */
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#define SSP2_APBCLK 0x01
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#define SSP2_FNCLK 0x02
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/* Register Base Addresses */
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#define ARMD1_DRAM_BASE 0xB0000000
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#define ARMD1_FEC_BASE 0xC0800000
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#define ARMD1_TIMER_BASE 0xD4014000
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#define ARMD1_APBC1_BASE 0xD4015000
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#define ARMD1_APBC2_BASE 0xD4015800
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#define ARMD1_UART1_BASE 0xD4017000
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#define ARMD1_UART2_BASE 0xD4018000
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#define ARMD1_GPIO_BASE 0xD4019000
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#define ARMD1_SSP1_BASE 0xD401B000
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#define ARMD1_SSP2_BASE 0xD401C000
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#define ARMD1_MFPR_BASE 0xD401E000
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#define ARMD1_SSP3_BASE 0xD401F000
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#define ARMD1_SSP4_BASE 0xD4020000
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#define ARMD1_SSP5_BASE 0xD4021000
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#define ARMD1_UART3_BASE 0xD4026000
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#define ARMD1_MPMU_BASE 0xD4050000
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#define ARMD1_APMU_BASE 0xD4282800
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#define ARMD1_CPU_BASE 0xD4282C00
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#endif /* CONFIG_ARMADA100 */
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#endif /* _ASM_ARCH_ARMADA100_H */
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