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https://github.com/brain-hackers/u-boot-brain
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f097532d27
Enable CONFIG_SYS_INIT_SP_BSS_OFFSET for all 64-bit Tegra boards. Place the stack/... 512KiB from the end of the U-Boot binary. This should be plenty to accommodate the current DTBs (max 64 KiB), early malloc region (6KiB), stack usage, and plenty of slack, while still not placing it too far away from the U-Boot binary. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
59 lines
1.9 KiB
C
59 lines
1.9 KiB
C
/*
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* Copyright 2013-2016, NVIDIA CORPORATION.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _TEGRA186_COMMON_H_
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#define _TEGRA186_COMMON_H_
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#include "tegra-common.h"
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/*
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* NS16550 Configuration
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*/
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#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_SYS_TEXT_BASE 0x80080000
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/* Generic Interrupt Controller */
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#define CONFIG_GICV2
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/*
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* Memory layout for where various images get loaded by boot scripts:
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*
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* scriptaddr can be pretty much anywhere that doesn't conflict with something
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* else. Put it above BOOTMAPSZ to eliminate conflicts.
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*
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* pxefile_addr_r can be pretty much anywhere that doesn't conflict with
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* something else. Put it above BOOTMAPSZ to eliminate conflicts.
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*
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* kernel_addr_r must be within the first 128M of RAM in order for the
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* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
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* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
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* should not overlap that area, or the kernel will have to copy itself
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* somewhere else before decompression. Similarly, the address of any other
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* data passed to the kernel shouldn't overlap the start of RAM. Pushing
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* this up to 16M allows for a sizable kernel to be decompressed below the
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* compressed load address.
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*
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* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
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* the compressed kernel to be up to 16M too.
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*
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* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
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* for the FDT/DTB to be up to 1M, which is hopefully plenty.
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*/
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#define CONFIG_LOADADDR 0x80080000
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#define MEM_LAYOUT_ENV_SETTINGS \
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"scriptaddr=0x90000000\0" \
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"pxefile_addr_r=0x90100000\0" \
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"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
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"fdt_addr_r=0x82000000\0" \
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"ramdisk_addr_r=0x82100000\0"
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#endif
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