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f090ea5aa5
There is a frequency/timing limitation for SOC and ARM, if SOC is OD voltage/OD freq, then ARM can't run at ND voltage/1.2Ghz, it may have timing risk from SOC to ARM. Current VDD_SOC is set to 0.95v OD voltage in SPL, and kernel will increase bus clocks to OD frequency before it increases ARM voltage. So to conform to the limitation, we'd better increases VDD_ARM to OD voltage in SPL. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
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| .. | ||
| imx8mp_evk.c | ||
| Kconfig | ||
| lpddr4_timing.c | ||
| MAINTAINERS | ||
| Makefile | ||
| spl.c | ||