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https://github.com/brain-hackers/u-boot-brain
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f089240128
The board/altera/socfpga directory is not a generic SoCFPGA machine anymore, but instead it represents the Altera SoCDK board. To make matters more complicated, it represents both CycloneV and ArriaV variant. On the other hand, nowadays, the content of this board directory is mostly comprised of QTS-generated header files, while all the generic code is in arch/arm/mach-socfpga already. Thus, this patch splits the board/altera/socfpga into a separate board directory for ArriaV SoCDK and CycloneV SoCDK, so that each can be populated with the correct QTS-generated header files for that particular board. Signed-off-by: Marek Vasut <marex@denx.de>
101 lines
4.8 KiB
C
101 lines
4.8 KiB
C
/*
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* Copyright Altera Corporation (C) 2012-2015
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* This file is autogenerated from tools provided by Altera.*/
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#ifndef __SDRAM_CONFIG_H
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#define __SDRAM_CONFIG_H
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
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#ifdef CONFIG_SOCFPGA_ARRIA5
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26
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#else
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
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#endif /* CONFIG_SOCFPGA_ARRIA5 */
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
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#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
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#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
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#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
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#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
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#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
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#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
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#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
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#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
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#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
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#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
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#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
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#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
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#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
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#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
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#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
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#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
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#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
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#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
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#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
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#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \
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0x01010101
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#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \
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0x01010101
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#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \
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0x0101
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
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#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0
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#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0
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#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0
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#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
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#endif /*#ifndef__SDRAM_CONFIG_H*/
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