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https://github.com/brain-hackers/u-boot-brain
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f089240128
The board/altera/socfpga directory is not a generic SoCFPGA machine anymore, but instead it represents the Altera SoCDK board. To make matters more complicated, it represents both CycloneV and ArriaV variant. On the other hand, nowadays, the content of this board directory is mostly comprised of QTS-generated header files, while all the generic code is in arch/arm/mach-socfpga already. Thus, this patch splits the board/altera/socfpga into a separate board directory for ArriaV SoCDK and CycloneV SoCDK, so that each can be populated with the correct QTS-generated header files for that particular board. Signed-off-by: Marek Vasut <marex@denx.de>
86 lines
1.6 KiB
C
86 lines
1.6 KiB
C
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/io.h>
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#include <usb.h>
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#include <usb/s3c_udc.h>
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#include <usb_mass_storage.h>
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#include <micrel.h>
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#include <netdev.h>
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#include <phy.h>
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DECLARE_GLOBAL_DATA_PTR;
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void s_init(void) {}
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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/* Address of boot parameters for ATAG (if ATAG is used) */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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/*
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* PHY configuration
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*/
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#ifdef CONFIG_PHY_MICREL_KSZ9021
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int board_phy_config(struct phy_device *phydev)
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{
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int ret;
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/*
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* These skew settings for the KSZ9021 ethernet phy is required for ethernet
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* to work reliably on most flavors of cyclone5 boards.
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*/
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ret = ksz9021_phy_extended_write(phydev,
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MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
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0x0);
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if (ret)
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return ret;
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ret = ksz9021_phy_extended_write(phydev,
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MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
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0x0);
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if (ret)
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return ret;
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ret = ksz9021_phy_extended_write(phydev,
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MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
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0xf0f0);
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if (ret)
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return ret;
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if (phydev->drv->config)
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return phydev->drv->config(phydev);
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return 0;
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}
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#endif
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#ifdef CONFIG_USB_GADGET
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struct s3c_plat_otg_data socfpga_otg_data = {
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.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
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.usb_gusbcfg = 0x1417,
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};
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int board_usb_init(int index, enum usb_init_type init)
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{
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return s3c_udc_probe(&socfpga_otg_data);
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}
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int g_dnl_board_usb_cable_connected(void)
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{
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return 1;
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}
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#endif
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