mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 06:06:15 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
251 lines
5.7 KiB
C
251 lines
5.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _HIGH_SPEED_ENV_SPEC_H
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#define _HIGH_SPEED_ENV_SPEC_H
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#include "seq_exec.h"
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/*
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* For setting or clearing a certain bit (bit is a number between 0 and 31)
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* in the data
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*/
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#define SET_BIT(data, bit) ((data) | (0x1 << (bit)))
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#define CLEAR_BIT(data, bit) ((data) & (~(0x1 << (bit))))
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#define MAX_SERDES_LANES 7 /* as in a39x */
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/* Serdes revision */
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/* Serdes revision 1.2 (for A38x-Z1) */
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#define MV_SERDES_REV_1_2 0x0
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/* Serdes revision 2.1 (for A39x-Z1, A38x-A0) */
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#define MV_SERDES_REV_2_1 0x1
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#define MV_SERDES_REV_NA 0xff
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#define SERDES_REGS_LANE_BASE_OFFSET(lane) (0x800 * (lane))
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#define PEX_X4_ENABLE_OFFS \
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(hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2 ? 18 : 31)
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/* Serdes lane types */
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enum serdes_type {
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PEX0,
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PEX1,
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PEX2,
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PEX3,
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SATA0,
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SATA1,
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SATA2,
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SATA3,
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SGMII0,
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SGMII1,
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SGMII2,
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QSGMII,
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USB3_HOST0,
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USB3_HOST1,
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USB3_DEVICE,
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SGMII3,
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XAUI,
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RXAUI,
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DEFAULT_SERDES,
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LAST_SERDES_TYPE
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};
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/* Serdes baud rates */
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enum serdes_speed {
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SERDES_SPEED_1_25_GBPS,
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SERDES_SPEED_1_5_GBPS,
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SERDES_SPEED_2_5_GBPS,
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SERDES_SPEED_3_GBPS,
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SERDES_SPEED_3_125_GBPS,
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SERDES_SPEED_5_GBPS,
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SERDES_SPEED_6_GBPS,
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SERDES_SPEED_6_25_GBPS,
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LAST_SERDES_SPEED
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};
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/* Serdes modes */
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enum serdes_mode {
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PEX_ROOT_COMPLEX_X1,
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PEX_ROOT_COMPLEX_X4,
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PEX_END_POINT_X1,
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PEX_END_POINT_X4,
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SERDES_DEFAULT_MODE, /* not pex */
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SERDES_LAST_MODE
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};
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struct serdes_map {
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enum serdes_type serdes_type;
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enum serdes_speed serdes_speed;
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enum serdes_mode serdes_mode;
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int swap_rx;
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int swap_tx;
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};
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/* Serdes ref clock options */
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enum ref_clock {
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REF_CLOCK_25MHZ,
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REF_CLOCK_100MHZ,
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REF_CLOCK_40MHZ,
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REF_CLOCK_UNSUPPORTED
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};
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/* Serdes sequences */
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enum serdes_seq {
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SATA_PORT_0_ONLY_POWER_UP_SEQ,
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SATA_PORT_1_ONLY_POWER_UP_SEQ,
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SATA_POWER_UP_SEQ,
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SATA_1_5_SPEED_CONFIG_SEQ,
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SATA_3_SPEED_CONFIG_SEQ,
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SATA_6_SPEED_CONFIG_SEQ,
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SATA_ELECTRICAL_CONFIG_SEQ,
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SATA_TX_CONFIG_SEQ1,
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SATA_PORT_0_ONLY_TX_CONFIG_SEQ,
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SATA_PORT_1_ONLY_TX_CONFIG_SEQ,
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SATA_TX_CONFIG_SEQ2,
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SGMII_POWER_UP_SEQ,
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SGMII_1_25_SPEED_CONFIG_SEQ,
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SGMII_3_125_SPEED_CONFIG_SEQ,
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SGMII_ELECTRICAL_CONFIG_SEQ,
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SGMII_TX_CONFIG_SEQ1,
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SGMII_TX_CONFIG_SEQ2,
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PEX_POWER_UP_SEQ,
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PEX_2_5_SPEED_CONFIG_SEQ,
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PEX_5_SPEED_CONFIG_SEQ,
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PEX_ELECTRICAL_CONFIG_SEQ,
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PEX_TX_CONFIG_SEQ1,
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PEX_TX_CONFIG_SEQ2,
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PEX_TX_CONFIG_SEQ3,
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PEX_BY_4_CONFIG_SEQ,
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PEX_CONFIG_REF_CLOCK_25MHZ_SEQ,
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PEX_CONFIG_REF_CLOCK_100MHZ_SEQ,
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PEX_CONFIG_REF_CLOCK_40MHZ_SEQ,
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USB3_POWER_UP_SEQ,
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USB3_HOST_SPEED_CONFIG_SEQ,
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USB3_DEVICE_SPEED_CONFIG_SEQ,
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USB3_ELECTRICAL_CONFIG_SEQ,
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USB3_TX_CONFIG_SEQ1,
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USB3_TX_CONFIG_SEQ2,
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USB3_TX_CONFIG_SEQ3,
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USB3_DEVICE_CONFIG_SEQ,
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USB2_POWER_UP_SEQ,
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SERDES_POWER_DOWN_SEQ,
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SGMII3_POWER_UP_SEQ,
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SGMII3_1_25_SPEED_CONFIG_SEQ,
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SGMII3_TX_CONFIG_SEQ1,
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SGMII3_TX_CONFIG_SEQ2,
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QSGMII_POWER_UP_SEQ,
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QSGMII_5_SPEED_CONFIG_SEQ,
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QSGMII_ELECTRICAL_CONFIG_SEQ,
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QSGMII_TX_CONFIG_SEQ1,
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QSGMII_TX_CONFIG_SEQ2,
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XAUI_POWER_UP_SEQ,
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XAUI_3_125_SPEED_CONFIG_SEQ,
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XAUI_ELECTRICAL_CONFIG_SEQ,
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XAUI_TX_CONFIG_SEQ1,
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XAUI_TX_CONFIG_SEQ2,
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RXAUI_POWER_UP_SEQ,
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RXAUI_6_25_SPEED_CONFIG_SEQ,
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RXAUI_ELECTRICAL_CONFIG_SEQ,
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RXAUI_TX_CONFIG_SEQ1,
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RXAUI_TX_CONFIG_SEQ2,
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SERDES_LAST_SEQ
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};
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/* The different sequence types for PEX and USB3 */
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enum {
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PEX,
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USB3,
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LAST_PEX_USB_SEQ_TYPE
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};
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enum {
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PEXSERDES_SPEED_2_5_GBPS,
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PEXSERDES_SPEED_5_GBPS,
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USB3SERDES_SPEED_5_GBPS_HOST,
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USB3SERDES_SPEED_5_GBPS_DEVICE,
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LAST_PEX_USB_SPEED_SEQ_TYPE
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};
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/* The different sequence types for SATA and SGMII */
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enum {
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SATA,
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SGMII,
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SGMII_3_125,
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LAST_SATA_SGMII_SEQ_TYPE
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};
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enum {
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QSGMII_SEQ_IDX,
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LAST_QSGMII_SEQ_TYPE
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};
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enum {
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XAUI_SEQ_IDX,
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RXAUI_SEQ_IDX,
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LAST_XAUI_RXAUI_SEQ_TYPE
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};
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enum {
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SATASERDES_SPEED_1_5_GBPS,
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SATASERDES_SPEED_3_GBPS,
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SATASERDES_SPEED_6_GBPS,
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SGMIISERDES_SPEED_1_25_GBPS,
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SGMIISERDES_SPEED_3_125_GBPS,
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LAST_SATA_SGMII_SPEED_SEQ_TYPE
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};
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extern u8 selectors_serdes_rev1_map[LAST_SERDES_TYPE][MAX_SERDES_LANES];
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extern u8 selectors_serdes_rev2_map[LAST_SERDES_TYPE][MAX_SERDES_LANES];
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u8 hws_ctrl_serdes_rev_get(void);
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int mv_update_serdes_select_phy_mode_seq(void);
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int hws_board_topology_load(struct serdes_map **serdes_map, u8 *count);
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enum serdes_seq serdes_type_and_speed_to_speed_seq(enum serdes_type serdes_type,
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enum serdes_speed baud_rate);
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int hws_serdes_seq_init(void);
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int hws_serdes_seq_db_init(void);
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int hws_power_up_serdes_lanes(struct serdes_map *serdes_map, u8 count);
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int hws_ctrl_high_speed_serdes_phy_config(void);
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int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up,
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enum serdes_type serdes_type,
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enum serdes_speed baud_rate,
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enum serdes_mode serdes_mode,
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enum ref_clock ref_clock);
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int serdes_power_up_ctrl_ext(u32 serdes_num, int serdes_power_up,
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enum serdes_type serdes_type,
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enum serdes_speed baud_rate,
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enum serdes_mode serdes_mode,
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enum ref_clock ref_clock);
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u32 hws_serdes_silicon_ref_clock_get(void);
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int hws_serdes_pex_ref_clock_get(enum serdes_type serdes_type,
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enum ref_clock *ref_clock);
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int hws_ref_clock_set(u32 serdes_num, enum serdes_type serdes_type,
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enum ref_clock ref_clock);
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int hws_update_serdes_phy_selectors(struct serdes_map *serdes_map, u8 count);
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u32 hws_serdes_get_phy_selector_val(int serdes_num,
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enum serdes_type serdes_type);
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u32 hws_serdes_get_ref_clock_val(enum serdes_type serdes_type);
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u32 hws_serdes_get_max_lane(void);
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int hws_get_ext_base_addr(u32 serdes_num, u32 base_addr, u32 unit_base_offset,
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u32 *unit_base_reg, u32 *unit_offset);
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int hws_pex_tx_config_seq(const struct serdes_map *serdes_map, u8 count);
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u32 hws_get_physical_serdes_num(u32 serdes_num);
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int hws_is_serdes_active(u8 lane_num);
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#endif /* _HIGH_SPEED_ENV_SPEC_H */
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