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![Stephen Warren](/assets/img/avatar_default.png)
A fair amount of the XUSB padctl driver will be common between Tegra124 and Tegra210. To avoid cut/paste between the two chips, create a new file that will contain the common code, and convert the Tegra124 code to use it. This change doesn't move every last piece of code that can/will be shared, but rather concentrates on moving code that can be moved with zero changes, so there are no other diffs mixed in. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
306 lines
6.3 KiB
C
306 lines
6.3 KiB
C
/*
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* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
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#include <common.h>
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#include <errno.h>
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#include "xusb-padctl-common.h"
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#include <asm/arch/clock.h>
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int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
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{
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if (phy && phy->ops && phy->ops->prepare)
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return phy->ops->prepare(phy);
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return phy ? -ENOSYS : -EINVAL;
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}
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int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
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{
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if (phy && phy->ops && phy->ops->enable)
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return phy->ops->enable(phy);
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return phy ? -ENOSYS : -EINVAL;
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}
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int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
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{
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if (phy && phy->ops && phy->ops->disable)
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return phy->ops->disable(phy);
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return phy ? -ENOSYS : -EINVAL;
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}
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int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
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{
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if (phy && phy->ops && phy->ops->unprepare)
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return phy->ops->unprepare(phy);
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return phy ? -ENOSYS : -EINVAL;
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}
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struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
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{
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struct tegra_xusb_phy *phy;
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int i;
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for (i = 0; i < padctl.socdata->num_phys; i++) {
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phy = &padctl.socdata->phys[i];
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if (phy->type != type)
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continue;
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return phy;
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}
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return NULL;
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}
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static const struct tegra_xusb_padctl_lane *
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tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name)
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{
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unsigned int i;
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for (i = 0; i < padctl->socdata->num_lanes; i++)
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if (strcmp(name, padctl->socdata->lanes[i].name) == 0)
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return &padctl->socdata->lanes[i];
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return NULL;
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}
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static int
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tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
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struct tegra_xusb_padctl_group *group,
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const void *fdt, int node)
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{
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unsigned int i;
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int len, err;
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group->name = fdt_get_name(fdt, node, &len);
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len = fdt_count_strings(fdt, node, "nvidia,lanes");
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if (len < 0) {
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error("failed to parse \"nvidia,lanes\" property");
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return -EINVAL;
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}
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group->num_pins = len;
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for (i = 0; i < group->num_pins; i++) {
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err = fdt_get_string_index(fdt, node, "nvidia,lanes", i,
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&group->pins[i]);
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if (err < 0) {
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error("failed to read string from \"nvidia,lanes\" property");
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return -EINVAL;
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}
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}
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group->num_pins = len;
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err = fdt_get_string(fdt, node, "nvidia,function", &group->func);
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if (err < 0) {
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error("failed to parse \"nvidia,func\" property");
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return -EINVAL;
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}
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group->iddq = fdtdec_get_int(fdt, node, "nvidia,iddq", -1);
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return 0;
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}
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static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl,
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const char *name)
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{
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unsigned int i;
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for (i = 0; i < padctl->socdata->num_functions; i++)
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if (strcmp(name, padctl->socdata->functions[i]) == 0)
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return i;
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return -ENOENT;
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}
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static int
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tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl,
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const struct tegra_xusb_padctl_lane *lane,
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const char *name)
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{
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unsigned int i;
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int func;
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func = tegra_xusb_padctl_find_function(padctl, name);
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if (func < 0)
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return func;
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for (i = 0; i < lane->num_funcs; i++)
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if (lane->funcs[i] == func)
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return i;
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return -ENOENT;
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}
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static int
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tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl,
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const struct tegra_xusb_padctl_group *group)
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{
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unsigned int i;
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for (i = 0; i < group->num_pins; i++) {
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const struct tegra_xusb_padctl_lane *lane;
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unsigned int func;
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u32 value;
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lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]);
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if (!lane) {
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error("no lane for pin %s", group->pins[i]);
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continue;
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}
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func = tegra_xusb_padctl_lane_find_function(padctl, lane,
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group->func);
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if (func < 0) {
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error("function %s invalid for lane %s: %d",
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group->func, lane->name, func);
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continue;
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}
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value = padctl_readl(padctl, lane->offset);
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/* set pin function */
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value &= ~(lane->mask << lane->shift);
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value |= func << lane->shift;
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/*
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* Set IDDQ if supported on the lane and specified in the
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* configuration.
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*/
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if (lane->iddq > 0 && group->iddq >= 0) {
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if (group->iddq != 0)
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value &= ~(1 << lane->iddq);
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else
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value |= 1 << lane->iddq;
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}
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padctl_writel(padctl, value, lane->offset);
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}
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return 0;
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}
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static int
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tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,
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struct tegra_xusb_padctl_config *config)
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{
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unsigned int i;
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for (i = 0; i < config->num_groups; i++) {
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const struct tegra_xusb_padctl_group *group;
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int err;
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group = &config->groups[i];
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err = tegra_xusb_padctl_group_apply(padctl, group);
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if (err < 0) {
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error("failed to apply group %s: %d",
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group->name, err);
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continue;
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}
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}
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return 0;
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}
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static int
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tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl,
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struct tegra_xusb_padctl_config *config,
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const void *fdt, int node)
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{
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int subnode;
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config->name = fdt_get_name(fdt, node, NULL);
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fdt_for_each_subnode(fdt, subnode, node) {
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struct tegra_xusb_padctl_group *group;
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int err;
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group = &config->groups[config->num_groups];
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err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt,
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subnode);
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if (err < 0) {
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error("failed to parse group %s", group->name);
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return err;
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}
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config->num_groups++;
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}
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return 0;
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}
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static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
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const void *fdt, int node)
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{
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int subnode, err;
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err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs);
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if (err < 0) {
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error("registers not found");
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return err;
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}
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fdt_for_each_subnode(fdt, subnode, node) {
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struct tegra_xusb_padctl_config *config = &padctl->config;
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err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt,
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subnode);
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if (err < 0) {
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error("failed to parse entry %s: %d",
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config->name, err);
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continue;
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}
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}
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return 0;
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}
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struct tegra_xusb_padctl padctl;
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int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count,
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const struct tegra_xusb_padctl_soc *socdata)
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{
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unsigned int i;
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int err;
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for (i = 0; i < count; i++) {
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if (!fdtdec_get_is_enabled(fdt, nodes[i]))
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continue;
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padctl.socdata = socdata;
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err = tegra_xusb_padctl_parse_dt(&padctl, fdt, nodes[i]);
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if (err < 0) {
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error("failed to parse DT: %d", err);
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continue;
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}
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/* deassert XUSB padctl reset */
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reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
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err = tegra_xusb_padctl_config_apply(&padctl, &padctl.config);
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if (err < 0) {
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error("failed to apply pinmux: %d", err);
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continue;
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}
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/* only a single instance is supported */
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break;
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}
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return 0;
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}
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