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https://github.com/brain-hackers/u-boot-brain
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![Kumar Gala](/assets/img/avatar_default.png)
Make it so we keep track of which LAWs have allocated and provide a function (set_next_law) which can allocate a LAW for us if one is free. In the future we will move to doing more "dynamic" LAW allocation since the majority of users dont really care about what LAW number they are at. Also, add CONFIG_MPC8540 or CONFIG_MPC8560 to those boards which needed them Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
328 lines
7.5 KiB
C
328 lines
7.5 KiB
C
/*
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* Copyright 2007 Freescale Semiconductor.
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*
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* (C) Copyright 2003 Motorola Inc.
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* Modified by Xianghua Xiao, X.Xiao@motorola.com
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/processor.h>
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#include <ioports.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/fsl_law.h>
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#include "mp.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_QE
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extern qe_iop_conf_t qe_iop_conf_tab[];
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extern void qe_config_iopin(u8 port, u8 pin, int dir,
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int open_drain, int assign);
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extern void qe_init(uint qe_base);
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extern void qe_reset(void);
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static void config_qe_ioports(void)
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{
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u8 port, pin;
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int dir, open_drain, assign;
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int i;
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for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
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port = qe_iop_conf_tab[i].port;
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pin = qe_iop_conf_tab[i].pin;
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dir = qe_iop_conf_tab[i].dir;
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open_drain = qe_iop_conf_tab[i].open_drain;
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assign = qe_iop_conf_tab[i].assign;
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qe_config_iopin(port, pin, dir, open_drain, assign);
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}
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}
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#endif
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#ifdef CONFIG_CPM2
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void config_8560_ioports (volatile ccsr_cpm_t * cpm)
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{
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int portnum;
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for (portnum = 0; portnum < 4; portnum++) {
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uint pmsk = 0,
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ppar = 0,
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psor = 0,
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pdir = 0,
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podr = 0,
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pdat = 0;
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iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
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iop_conf_t *eiopc = iopc + 32;
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uint msk = 1;
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/*
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* NOTE:
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* index 0 refers to pin 31,
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* index 31 refers to pin 0
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*/
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while (iopc < eiopc) {
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if (iopc->conf) {
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pmsk |= msk;
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if (iopc->ppar)
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ppar |= msk;
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if (iopc->psor)
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psor |= msk;
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if (iopc->pdir)
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pdir |= msk;
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if (iopc->podr)
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podr |= msk;
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if (iopc->pdat)
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pdat |= msk;
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}
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msk <<= 1;
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iopc++;
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}
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if (pmsk != 0) {
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volatile ioport_t *iop = ioport_addr (cpm, portnum);
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uint tpmsk = ~pmsk;
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/*
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* the (somewhat confused) paragraph at the
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* bottom of page 35-5 warns that there might
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* be "unknown behaviour" when programming
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* PSORx and PDIRx, if PPARx = 1, so I
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* decided this meant I had to disable the
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* dedicated function first, and enable it
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* last.
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*/
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iop->ppar &= tpmsk;
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iop->psor = (iop->psor & tpmsk) | psor;
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iop->podr = (iop->podr & tpmsk) | podr;
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iop->pdat = (iop->pdat & tpmsk) | pdat;
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iop->pdir = (iop->pdir & tpmsk) | pdir;
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iop->ppar |= ppar;
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}
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}
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}
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#endif
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/* We run cpu_init_early_f in AS = 1 */
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void cpu_init_early_f(void)
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{
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set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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1, 0, BOOKE_PAGESZ_4K, 0);
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/* set up CCSR if we want it moved */
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#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS)
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{
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u32 temp;
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set_tlb(0, CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_DEFAULT,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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1, 1, BOOKE_PAGESZ_4K, 0);
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temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT);
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out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_PHYS >> 12);
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temp = in_be32((volatile u32 *)CFG_CCSRBAR);
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}
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#endif
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
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/* Clear initial global data */
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memset ((void *) gd, 0, sizeof (gd_t));
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init_laws();
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invalidate_tlb(0);
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init_tlbs();
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}
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/*
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* Breathe some life into the CPU...
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*
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* Set up the memory map
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* initialize a bunch of registers
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*/
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void cpu_init_f (void)
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{
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volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
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extern void m8560_cpm_reset (void);
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disable_tlb(14);
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disable_tlb(15);
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#ifdef CONFIG_CPM2
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config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR);
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#endif
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/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
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* addresses - these have to be modified later when FLASH size
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* has been determined
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*/
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#if defined(CFG_OR0_REMAP)
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memctl->or0 = CFG_OR0_REMAP;
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#endif
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#if defined(CFG_OR1_REMAP)
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memctl->or1 = CFG_OR1_REMAP;
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#endif
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/* now restrict to preliminary range */
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/* if cs1 is already set via debugger, leave cs0/cs1 alone */
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if (! memctl->br1 & 1) {
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#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
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memctl->br0 = CFG_BR0_PRELIM;
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memctl->or0 = CFG_OR0_PRELIM;
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#endif
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#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
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memctl->or1 = CFG_OR1_PRELIM;
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memctl->br1 = CFG_BR1_PRELIM;
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#endif
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}
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#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
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memctl->or2 = CFG_OR2_PRELIM;
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memctl->br2 = CFG_BR2_PRELIM;
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#endif
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#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
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memctl->or3 = CFG_OR3_PRELIM;
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memctl->br3 = CFG_BR3_PRELIM;
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#endif
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#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
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memctl->or4 = CFG_OR4_PRELIM;
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memctl->br4 = CFG_BR4_PRELIM;
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#endif
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#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
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memctl->or5 = CFG_OR5_PRELIM;
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memctl->br5 = CFG_BR5_PRELIM;
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#endif
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#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
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memctl->or6 = CFG_OR6_PRELIM;
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memctl->br6 = CFG_BR6_PRELIM;
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#endif
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#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
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memctl->or7 = CFG_OR7_PRELIM;
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memctl->br7 = CFG_BR7_PRELIM;
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#endif
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#if defined(CONFIG_CPM2)
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m8560_cpm_reset();
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#endif
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#ifdef CONFIG_QE
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/* Config QE ioports */
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config_qe_ioports();
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#endif
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}
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/*
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* Initialize L2 as cache.
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*
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* The newer 8548, etc, parts have twice as much cache, but
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* use the same bit-encoding as the older 8555, etc, parts.
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*
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*/
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int cpu_init_r(void)
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{
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puts ("L2: ");
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#if defined(CONFIG_L2_CACHE)
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volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
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volatile uint cache_ctl;
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uint svr, ver;
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uint l2srbar;
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svr = get_svr();
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ver = SVR_SOC_VER(svr);
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asm("msync;isync");
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cache_ctl = l2cache->l2ctl;
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switch (cache_ctl & 0x30000000) {
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case 0x20000000:
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if (ver == SVR_8548 || ver == SVR_8548_E ||
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ver == SVR_8544 || ver == SVR_8568_E) {
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puts ("512 KB ");
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/* set L2E=1, L2I=1, & L2SRAM=0 */
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cache_ctl = 0xc0000000;
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} else {
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puts("256 KB ");
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/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
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cache_ctl = 0xc8000000;
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}
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break;
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case 0x10000000:
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puts("256 KB ");
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if (ver == SVR_8544 || ver == SVR_8544_E) {
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cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
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}
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break;
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case 0x30000000:
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case 0x00000000:
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default:
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printf(" unknown size (0x%08x)\n", cache_ctl);
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return -1;
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}
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if (l2cache->l2ctl & 0x80000000) {
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puts("already enabled");
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l2srbar = l2cache->l2srbar0;
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#ifdef CFG_INIT_L2_ADDR
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if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) {
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l2srbar = CFG_INIT_L2_ADDR;
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l2cache->l2srbar0 = l2srbar;
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printf("moving to 0x%08x", CFG_INIT_L2_ADDR);
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}
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#endif /* CFG_INIT_L2_ADDR */
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puts("\n");
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} else {
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asm("msync;isync");
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l2cache->l2ctl = cache_ctl; /* invalidate & enable */
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asm("msync;isync");
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puts("enabled\n");
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}
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#else
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puts("disabled\n");
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#endif
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#ifdef CONFIG_QE
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uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */
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qe_init(qe_base);
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qe_reset();
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#endif
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#if defined(CONFIG_MP)
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setup_mp();
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#endif
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return 0;
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}
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