Simon Glass 0990c894cc x86: fsp: Support a warning message when DRAM init is slow ... With DDR4, Intel SOCs take quite a long time to init their memory. During this time, if the user is watching, it looks like SPL has hung. Add a message in this case. This works by adding a return code to fspm_update_config() that indicates whether MRC data was found and a new property to the device tree. Also add one more debug message while starting. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>		2020-07-17 14:32:24 +08:00
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fsp_common.c	x86: fsp: Add FSP2 base support	2019-12-15 11:44:16 +08:00
fsp_dram.c	x86: Avoid #ifdef with CONFIG_HAVE_ACPI_RESUME	2020-07-17 14:32:24 +08:00
fsp_init.c	cbfs: Don't require the CBFS size with cbfs_init_mem()	2020-05-27 14:40:09 +08:00
fsp_meminit.c	x86: fsp: Support a warning message when DRAM init is slow	2020-07-17 14:32:24 +08:00
fsp_silicon_init.c	common: Drop log.h from common header	2020-05-18 21:19:18 -04:00
fsp_support.c	common: Drop log.h from common header	2020-05-18 21:19:18 -04:00
Makefile	x86: fsp: Add FSP2 base support	2019-12-15 11:44:16 +08:00