mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
a47a12becf
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
155 lines
4.4 KiB
C
155 lines
4.4 KiB
C
/*
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* (C) Copyright 2004
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* Tolunay Orkun, Nextio Inc., torkun@nextio.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <ppc4xx_enet.h>
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void sdram_init(void);
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/*
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* board_early_init_f: do early board initialization
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*
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*/
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int board_early_init_f(void)
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{
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/*-------------------------------------------------------------------------+
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| Interrupt controller setup for the Walnut board.
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| Note: IRQ 0-15 405GP internally generated; active high; level sensitive
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| IRQ 16 405GP internally generated; active low; level sensitive
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| IRQ 17-24 RESERVED
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| IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
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| IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
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| IRQ 27 (EXT IRQ 2) Not Used
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| IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
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| IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
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| IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
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| IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
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| Note for Walnut board:
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| An interrupt taken for the FPGA (IRQ 25) indicates that either
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| the Mouse, Keyboard, IRDA, or External Expansion caused the
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| interrupt. The FPGA must be read to determine which device
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| caused the interrupt. The default setting of the FPGA clears
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+-------------------------------------------------------------------------*/
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr (UIC0ER, 0x00000000); /* disable all ints */
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mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
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mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */
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mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
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mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */
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return 0; /* success */
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}
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/*
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* checkboard: identify/verify the board we are running
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*
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* Remark: we just assume it is correct board here!
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*
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*/
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int checkboard(void)
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{
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printf("BOARD: Cogent CSB472\n");
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return 0; /* success */
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}
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/*
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* initram: Determine the size of mounted DRAM
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*
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* Size is determined by reading SDRAM configuration registers as
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* configured by initialization code
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*
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*/
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phys_size_t initdram (int board_type)
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{
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ulong tot_size;
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ulong bank_size;
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ulong tmp;
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/*
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* ToDo: Move the asm init routine sdram_init() to this C file,
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* or even better use some common ppc4xx code available
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* in arch/powerpc/cpu/ppc4xx
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*/
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sdram_init();
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tot_size = 0;
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
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tmp = mfdcr (SDRAM0_CFGDATA);
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if (tmp & 0x00000001) {
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
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tot_size += bank_size;
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}
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
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tmp = mfdcr (SDRAM0_CFGDATA);
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if (tmp & 0x00000001) {
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
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tot_size += bank_size;
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}
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
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tmp = mfdcr (SDRAM0_CFGDATA);
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if (tmp & 0x00000001) {
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
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tot_size += bank_size;
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}
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
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tmp = mfdcr (SDRAM0_CFGDATA);
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if (tmp & 0x00000001) {
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
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tot_size += bank_size;
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}
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return tot_size;
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}
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/*
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* last_stage_init: final configurations (such as PHY etc)
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*
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*/
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int last_stage_init(void)
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{
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/* initialize the PHY */
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miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
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/* AUTO neg */
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miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR,
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PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
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/* LEDs */
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miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);
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return 0; /* success */
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}
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