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ef9a1f9a4f
u-boot-brain/board/freescale/t4qds
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Shaohui Xie ef9a1f9a4f powerpc/t4240: updated rcw_cfg to align with default hardware configuration 
Default configuration has been changed, the most important one is DDR
ref_clock which is changed from 66.67MHz to 133.33MHz. so the ratio need to
change from 24x to 12x to keep the DDR frequency. There are also some
other optimise to align with default configuration.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2013-10-16 16:13:12 -07:00
..
ddr.c powerpc/T4240EMU: Add T4240EMU target 2013-08-09 12:41:39 -07:00
ddr.h powerpc/mpc85xx: Cleanup license header in source files 2013-08-12 15:04:24 -07:00
eth.c powerpc/t4240: add QSGMII interface support 2013-08-20 10:46:48 -07:00
law.c powerpc/T4240EMU: Add T4240EMU target 2013-08-09 12:41:39 -07:00
Makefile powerpc/T4240EMU: Add T4240EMU target 2013-08-09 12:41:39 -07:00
pci.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
t4_pbi.cfg T4240/ramboot: enable PBL tool for T4240 2013-05-24 16:54:10 -05:00
t4_rcw.cfg powerpc/t4240: updated rcw_cfg to align with default hardware configuration 2013-10-16 16:13:12 -07:00
t4qds.h Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
t4240emu.c powerpc/mpc85xx: Cleanup license header in source files 2013-08-12 15:04:24 -07:00
t4240qds_qixis.h Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
t4240qds.c powerpc/t4240: fix lanes routing for QSGMII protocols 2013-08-20 10:46:39 -07:00
tlb.c powerpc/T4240EMU: Add T4240EMU target 2013-08-09 12:41:39 -07:00