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![Patrick Delaunay](/assets/img/avatar_default.png)
Add support of STM32MP1 rtc driver. Enable it for basic and trusted configurations. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
324 lines
7.8 KiB
C
324 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <rtc.h>
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#include <asm/io.h>
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#include <linux/iopoll.h>
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#define STM32_RTC_TR 0x00
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#define STM32_RTC_DR 0x04
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#define STM32_RTC_ISR 0x0C
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#define STM32_RTC_PRER 0x10
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#define STM32_RTC_CR 0x18
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#define STM32_RTC_WPR 0x24
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/* STM32_RTC_TR bit fields */
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#define STM32_RTC_SEC_SHIFT 0
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#define STM32_RTC_SEC GENMASK(6, 0)
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#define STM32_RTC_MIN_SHIFT 8
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#define STM32_RTC_MIN GENMASK(14, 8)
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#define STM32_RTC_HOUR_SHIFT 16
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#define STM32_RTC_HOUR GENMASK(21, 16)
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/* STM32_RTC_DR bit fields */
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#define STM32_RTC_DATE_SHIFT 0
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#define STM32_RTC_DATE GENMASK(5, 0)
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#define STM32_RTC_MONTH_SHIFT 8
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#define STM32_RTC_MONTH GENMASK(12, 8)
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#define STM32_RTC_WDAY_SHIFT 13
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#define STM32_RTC_WDAY GENMASK(15, 13)
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#define STM32_RTC_YEAR_SHIFT 16
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#define STM32_RTC_YEAR GENMASK(23, 16)
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/* STM32_RTC_CR bit fields */
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#define STM32_RTC_CR_FMT BIT(6)
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/* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */
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#define STM32_RTC_ISR_INITS BIT(4)
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#define STM32_RTC_ISR_RSF BIT(5)
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#define STM32_RTC_ISR_INITF BIT(6)
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#define STM32_RTC_ISR_INIT BIT(7)
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/* STM32_RTC_PRER bit fields */
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#define STM32_RTC_PRER_PRED_S_SHIFT 0
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#define STM32_RTC_PRER_PRED_S GENMASK(14, 0)
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#define STM32_RTC_PRER_PRED_A_SHIFT 16
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#define STM32_RTC_PRER_PRED_A GENMASK(22, 16)
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/* STM32_RTC_WPR key constants */
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#define RTC_WPR_1ST_KEY 0xCA
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#define RTC_WPR_2ND_KEY 0x53
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#define RTC_WPR_WRONG_KEY 0xFF
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struct stm32_rtc_priv {
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fdt_addr_t base;
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};
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static int stm32_rtc_get(struct udevice *dev, struct rtc_time *tm)
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{
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struct stm32_rtc_priv *priv = dev_get_priv(dev);
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u32 tr, dr;
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tr = readl(priv->base + STM32_RTC_TR);
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dr = readl(priv->base + STM32_RTC_DR);
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tm->tm_sec = bcd2bin((tr & STM32_RTC_SEC) >> STM32_RTC_SEC_SHIFT);
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tm->tm_min = bcd2bin((tr & STM32_RTC_MIN) >> STM32_RTC_MIN_SHIFT);
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tm->tm_hour = bcd2bin((tr & STM32_RTC_HOUR) >> STM32_RTC_HOUR_SHIFT);
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tm->tm_mday = bcd2bin((dr & STM32_RTC_DATE) >> STM32_RTC_DATE_SHIFT);
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tm->tm_mon = bcd2bin((dr & STM32_RTC_MONTH) >> STM32_RTC_MONTH_SHIFT);
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tm->tm_year = bcd2bin((dr & STM32_RTC_YEAR) >> STM32_RTC_YEAR_SHIFT);
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tm->tm_wday = bcd2bin((dr & STM32_RTC_WDAY) >> STM32_RTC_WDAY_SHIFT);
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tm->tm_yday = 0;
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tm->tm_isdst = 0;
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dev_dbg(dev, "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
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tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
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tm->tm_hour, tm->tm_min, tm->tm_sec);
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return 0;
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}
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static void stm32_rtc_unlock(struct udevice *dev)
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{
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struct stm32_rtc_priv *priv = dev_get_priv(dev);
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writel(RTC_WPR_1ST_KEY, priv->base + STM32_RTC_WPR);
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writel(RTC_WPR_2ND_KEY, priv->base + STM32_RTC_WPR);
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}
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static void stm32_rtc_lock(struct udevice *dev)
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{
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struct stm32_rtc_priv *priv = dev_get_priv(dev);
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writel(RTC_WPR_WRONG_KEY, priv->base + STM32_RTC_WPR);
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}
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static int stm32_rtc_enter_init_mode(struct udevice *dev)
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{
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struct stm32_rtc_priv *priv = dev_get_priv(dev);
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u32 isr = readl(priv->base + STM32_RTC_ISR);
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if (!(isr & STM32_RTC_ISR_INITF)) {
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isr |= STM32_RTC_ISR_INIT;
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writel(isr, priv->base + STM32_RTC_ISR);
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return readl_poll_timeout(priv->base + STM32_RTC_ISR,
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isr,
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(isr & STM32_RTC_ISR_INITF),
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100000);
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}
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return 0;
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}
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static int stm32_rtc_wait_sync(struct udevice *dev)
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{
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struct stm32_rtc_priv *priv = dev_get_priv(dev);
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u32 isr = readl(priv->base + STM32_RTC_ISR);
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isr &= ~STM32_RTC_ISR_RSF;
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writel(isr, priv->base + STM32_RTC_ISR);
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/*
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* Wait for RSF to be set to ensure the calendar registers are
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* synchronised, it takes around 2 rtc_ck clock cycles
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*/
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return readl_poll_timeout(priv->base + STM32_RTC_ISR,
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isr, (isr & STM32_RTC_ISR_RSF),
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100000);
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}
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static void stm32_rtc_exit_init_mode(struct udevice *dev)
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{
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struct stm32_rtc_priv *priv = dev_get_priv(dev);
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u32 isr = readl(priv->base + STM32_RTC_ISR);
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isr &= ~STM32_RTC_ISR_INIT;
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writel(isr, priv->base + STM32_RTC_ISR);
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}
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static int stm32_rtc_set_time(struct udevice *dev, u32 time, u32 date)
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{
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struct stm32_rtc_priv *priv = dev_get_priv(dev);
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int ret;
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stm32_rtc_unlock(dev);
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ret = stm32_rtc_enter_init_mode(dev);
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if (ret)
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goto lock;
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writel(time, priv->base + STM32_RTC_TR);
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writel(date, priv->base + STM32_RTC_DR);
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stm32_rtc_exit_init_mode(dev);
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ret = stm32_rtc_wait_sync(dev);
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lock:
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stm32_rtc_lock(dev);
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return ret;
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}
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static int stm32_rtc_set(struct udevice *dev, const struct rtc_time *tm)
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{
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u32 t, d;
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dev_dbg(dev, "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
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tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
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tm->tm_hour, tm->tm_min, tm->tm_sec);
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/* Time in BCD format */
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t = (bin2bcd(tm->tm_sec) << STM32_RTC_SEC_SHIFT) & STM32_RTC_SEC;
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t |= (bin2bcd(tm->tm_min) << STM32_RTC_MIN_SHIFT) & STM32_RTC_MIN;
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t |= (bin2bcd(tm->tm_hour) << STM32_RTC_HOUR_SHIFT) & STM32_RTC_HOUR;
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/* Date in BCD format */
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d = (bin2bcd(tm->tm_mday) << STM32_RTC_DATE_SHIFT) & STM32_RTC_DATE;
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d |= (bin2bcd(tm->tm_mon) << STM32_RTC_MONTH_SHIFT) & STM32_RTC_MONTH;
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d |= (bin2bcd(tm->tm_year) << STM32_RTC_YEAR_SHIFT) & STM32_RTC_YEAR;
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d |= (bin2bcd(tm->tm_wday) << STM32_RTC_WDAY_SHIFT) & STM32_RTC_WDAY;
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return stm32_rtc_set_time(dev, t, d);
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}
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static int stm32_rtc_reset(struct udevice *dev)
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{
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dev_dbg(dev, "Reset DATE\n");
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return stm32_rtc_set_time(dev, 0, 0);
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}
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static int stm32_rtc_init(struct udevice *dev)
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{
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struct stm32_rtc_priv *priv = dev_get_priv(dev);
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unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
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unsigned int rate;
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struct clk clk;
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int ret;
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u32 isr = readl(priv->base + STM32_RTC_ISR);
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if (isr & STM32_RTC_ISR_INITS)
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return 0;
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ret = clk_get_by_index(dev, 1, &clk);
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if (ret)
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return ret;
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ret = clk_enable(&clk);
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if (ret) {
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clk_free(&clk);
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return ret;
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}
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rate = clk_get_rate(&clk);
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/* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
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pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
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pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
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for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) {
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pred_s = (rate / (pred_a + 1)) - 1;
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if (((pred_s + 1) * (pred_a + 1)) == rate)
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break;
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}
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/*
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* Can't find a 1Hz, so give priority to RTC power consumption
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* by choosing the higher possible value for prediv_a
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*/
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if (pred_s > pred_s_max || pred_a > pred_a_max) {
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pred_a = pred_a_max;
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pred_s = (rate / (pred_a + 1)) - 1;
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}
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stm32_rtc_unlock(dev);
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ret = stm32_rtc_enter_init_mode(dev);
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if (ret) {
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dev_err(dev,
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"Can't enter in init mode. Prescaler config failed.\n");
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goto unlock;
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}
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prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S;
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prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A;
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writel(prer, priv->base + STM32_RTC_PRER);
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/* Force 24h time format */
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cr = readl(priv->base + STM32_RTC_CR);
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cr &= ~STM32_RTC_CR_FMT;
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writel(cr, priv->base + STM32_RTC_CR);
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stm32_rtc_exit_init_mode(dev);
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ret = stm32_rtc_wait_sync(dev);
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unlock:
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stm32_rtc_lock(dev);
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if (ret) {
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clk_disable(&clk);
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clk_free(&clk);
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}
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return ret;
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}
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static int stm32_rtc_probe(struct udevice *dev)
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{
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struct stm32_rtc_priv *priv = dev_get_priv(dev);
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struct clk clk;
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int ret;
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priv->base = dev_read_addr(dev);
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if (priv->base == FDT_ADDR_T_NONE)
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return -EINVAL;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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ret = clk_enable(&clk);
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if (ret) {
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clk_free(&clk);
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return ret;
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}
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ret = stm32_rtc_init(dev);
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if (ret) {
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clk_disable(&clk);
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clk_free(&clk);
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}
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return ret;
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}
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static const struct rtc_ops stm32_rtc_ops = {
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.get = stm32_rtc_get,
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.set = stm32_rtc_set,
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.reset = stm32_rtc_reset,
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};
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static const struct udevice_id stm32_rtc_ids[] = {
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{ .compatible = "st,stm32mp1-rtc" },
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{ }
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};
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U_BOOT_DRIVER(rtc_stm32) = {
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.name = "rtc-stm32",
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.id = UCLASS_RTC,
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.probe = stm32_rtc_probe,
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.of_match = stm32_rtc_ids,
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.ops = &stm32_rtc_ops,
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.priv_auto_alloc_size = sizeof(struct stm32_rtc_priv),
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};
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