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cf8ddacffc
T1042 has internal display interface unit (DIU) for driving video.
T1042RDB supports video mode via
-LCD using TI enconder
-HDMI type interface via HDMI encoder
Chrontel, CH7301C encoder which is I2C programmable is used
as HDMI connector on T1042RDB.
This patch add support to
-enable Video interface for T1042RDB
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1042
-program HDMI encoder via I2C on board
This patch refer to the upstream diu patch
(337b0c52b3) for T1040qds.
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
[York Sun: resolve conflict and move changes to T104xRDB.h]
Reviewed-by: York Sun <yorksun@freescale.com>
85 lines
2.1 KiB
C
85 lines
2.1 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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* Author: Priyanka Jain <Priyanka.Jain@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/io.h>
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#include <common.h>
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#include <command.h>
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#include <fsl_diu_fb.h>
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#include <linux/ctype.h>
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#include <video_fb.h>
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#include "../common/diu_ch7301.h"
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#include "cpld.h"
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#include "t104xrdb.h"
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/*
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* DIU Area Descriptor
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*
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* Note that we need to byte-swap the value before it's written to the AD
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* register. So even though the registers don't look like they're in the same
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* bit positions as they are on the MPC8610, the same value is written to the
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* AD register on the MPC8610 and on the P1022.
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*/
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#define AD_BYTE_F 0x10000000
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#define AD_ALPHA_C_SHIFT 25
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#define AD_BLUE_C_SHIFT 23
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#define AD_GREEN_C_SHIFT 21
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#define AD_RED_C_SHIFT 19
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#define AD_PIXEL_S_SHIFT 16
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#define AD_COMP_3_SHIFT 12
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#define AD_COMP_2_SHIFT 8
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#define AD_COMP_1_SHIFT 4
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#define AD_COMP_0_SHIFT 0
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void diu_set_pixel_clock(unsigned int pixclock)
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{
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unsigned long speed_ccb, temp;
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u32 pixval;
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int ret;
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speed_ccb = get_bus_freq(0);
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temp = 1000000000 / pixclock;
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temp *= 1000;
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pixval = speed_ccb / temp;
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/* Program HDMI encoder */
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ret = diu_set_dvi_encoder(temp);
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if (ret) {
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puts("Failed to set DVI encoder\n");
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return;
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}
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/* Program pixel clock */
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out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
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((pixval << PXCK_BITS_START) & PXCK_MASK));
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/* enable clock*/
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out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
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((pixval << PXCK_BITS_START) & PXCK_MASK));
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}
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int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
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{
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u32 pixel_format;
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u8 sw;
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/*Configure Display ouput port as HDMI*/
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sw = CPLD_READ(sfp_ctl_status);
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CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP));
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pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
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(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
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(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
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(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
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(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
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printf("DIU: Switching to monitor DVI @ %ux%u\n", xres, yres);
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return fsl_diu_init(xres, yres, pixel_format, 0);
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}
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