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https://github.com/brain-hackers/u-boot-brain
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![Ley Foon Tan](/assets/img/avatar_default.png)
Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
177 lines
4.4 KiB
C
177 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
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*
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*/
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#ifndef _SYSTEM_MANAGER_S10_
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#define _SYSTEM_MANAGER_S10_
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void sysmgr_pinmux_init(void);
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void populate_sysmgr_fpgaintf_module(void);
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void populate_sysmgr_pinmux(void);
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void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
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void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
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void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
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void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
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struct socfpga_system_manager {
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/* System Manager Module */
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u32 siliconid1; /* 0x00 */
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u32 siliconid2;
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u32 wddbg;
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u32 _pad_0xc;
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u32 mpu_status; /* 0x10 */
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u32 mpu_ace;
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u32 _pad_0x18_0x1c[2];
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u32 dma; /* 0x20 */
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u32 dma_periph;
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/* SDMMC Controller Group */
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u32 sdmmcgrp_ctrl;
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u32 sdmmcgrp_l3master;
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/* NAND Flash Controller Register Group */
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u32 nandgrp_bootstrap; /* 0x30 */
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u32 nandgrp_l3master;
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/* USB Controller Group */
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u32 usb0_l3master;
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u32 usb1_l3master;
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/* EMAC Group */
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u32 emac_gbl; /* 0x40 */
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u32 emac0;
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u32 emac1;
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u32 emac2;
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u32 emac0_ace; /* 0x50 */
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u32 emac1_ace;
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u32 emac2_ace;
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u32 nand_axuser;
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u32 _pad_0x60_0x64[2]; /* 0x60 */
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/* FPGA interface Group */
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u32 fpgaintf_en_1;
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u32 fpgaintf_en_2;
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u32 fpgaintf_en_3; /* 0x70 */
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u32 dma_l3master;
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u32 etr_l3master;
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u32 _pad_0x7c;
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u32 sec_ctrl_slt; /* 0x80 */
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u32 osc_trim;
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u32 _pad_0x88_0x8c[2];
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/* ECC Group */
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u32 ecc_intmask_value; /* 0x90 */
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u32 ecc_intmask_set;
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u32 ecc_intmask_clr;
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u32 ecc_intstatus_serr;
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u32 ecc_intstatus_derr; /* 0xa0 */
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u32 _pad_0xa4_0xac[3];
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u32 noc_addr_remap; /* 0xb0 */
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u32 hmc_clk;
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u32 io_pa_ctrl;
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u32 _pad_0xbc;
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/* NOC Group */
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u32 noc_timeout; /* 0xc0 */
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u32 noc_idlereq_set;
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u32 noc_idlereq_clr;
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u32 noc_idlereq_value;
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u32 noc_idleack; /* 0xd0 */
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u32 noc_idlestatus;
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u32 fpga2soc_ctrl;
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u32 fpga_config;
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u32 iocsrclk_gate; /* 0xe0 */
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u32 gpo;
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u32 gpi;
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u32 _pad_0xec;
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u32 mpu; /* 0xf0 */
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u32 sdm_hps_spare;
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u32 hps_sdm_spare;
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u32 _pad_0xfc_0x1fc[65];
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/* Boot scratch register group */
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u32 boot_scratch_cold0; /* 0x200 */
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u32 boot_scratch_cold1;
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u32 boot_scratch_cold2;
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u32 boot_scratch_cold3;
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u32 boot_scratch_cold4; /* 0x210 */
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u32 boot_scratch_cold5;
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u32 boot_scratch_cold6;
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u32 boot_scratch_cold7;
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u32 boot_scratch_cold8; /* 0x220 */
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u32 boot_scratch_cold9;
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u32 _pad_0x228_0xffc[886];
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/* Pin select and pin control group */
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u32 pinsel0[40]; /* 0x1000 */
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u32 _pad_0x10a0_0x10fc[24];
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u32 pinsel40[8];
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u32 _pad_0x1120_0x112c[4];
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u32 ioctrl0[28];
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u32 _pad_0x11a0_0x11fc[24];
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u32 ioctrl28[20];
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u32 _pad_0x1250_0x12fc[44];
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/* Use FPGA mux */
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u32 rgmii0usefpga; /* 0x1300 */
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u32 rgmii1usefpga;
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u32 rgmii2usefpga;
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u32 i2c0usefpga;
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u32 i2c1usefpga;
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u32 i2c_emac0_usefpga;
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u32 i2c_emac1_usefpga;
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u32 i2c_emac2_usefpga;
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u32 nandusefpga;
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u32 _pad_0x1324;
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u32 spim0usefpga;
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u32 spim1usefpga;
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u32 spis0usefpga;
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u32 spis1usefpga;
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u32 uart0usefpga;
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u32 uart1usefpga;
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u32 mdio0usefpga;
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u32 mdio1usefpga;
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u32 mdio2usefpga;
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u32 _pad_0x134c;
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u32 jtagusefpga;
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u32 sdmmcusefpga;
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u32 hps_osc_clk;
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u32 _pad_0x135c_0x13fc[41];
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u32 iodelay0[40];
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u32 _pad_0x14a0_0x14fc[24];
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u32 iodelay40[8];
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};
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#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
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#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
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#define SYSMGR_ECC_OCRAM_EN BIT(0)
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#define SYSMGR_ECC_OCRAM_SERR BIT(3)
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#define SYSMGR_ECC_OCRAM_DERR BIT(4)
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#define SYSMGR_FPGAINTF_USEFPGA 0x1
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#define SYSMGR_FPGAINTF_NAND BIT(4)
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#define SYSMGR_FPGAINTF_SDMMC BIT(8)
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#define SYSMGR_FPGAINTF_SPIM0 BIT(16)
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#define SYSMGR_FPGAINTF_SPIM1 BIT(24)
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#define SYSMGR_FPGAINTF_EMAC0 BIT(0)
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#define SYSMGR_FPGAINTF_EMAC1 BIT(8)
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#define SYSMGR_FPGAINTF_EMAC2 BIT(16)
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#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
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#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
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/* EMAC Group Bit definitions */
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
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#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
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#define SYSMGR_NOC_H2F_MSK 0x00000001
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#define SYSMGR_NOC_LWH2F_MSK 0x00000010
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#define SYSMGR_HMC_CLK_STATUS_MSK 0x00000001
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#define SYSMGR_DMA_IRQ_NS 0xFF000000
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#define SYSMGR_DMA_MGR_NS 0x00010000
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#define SYSMGR_DMAPERIPH_ALL_NS 0xFFFFFFFF
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#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F
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#endif /* _SYSTEM_MANAGER_S10_ */
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