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![Ley Foon Tan](/assets/img/avatar_default.png)
Add Clock Manager driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
211 lines
4.9 KiB
C
211 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
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*
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*/
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#ifndef _CLOCK_MANAGER_S10_
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#define _CLOCK_MANAGER_S10_
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/* Clock speed accessors */
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unsigned long cm_get_mpu_clk_hz(void);
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unsigned long cm_get_sdram_clk_hz(void);
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unsigned int cm_get_l4_sp_clk_hz(void);
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unsigned int cm_get_mmc_controller_clk_hz(void);
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unsigned int cm_get_qspi_controller_clk_hz(void);
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unsigned int cm_get_spi_controller_clk_hz(void);
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const unsigned int cm_get_osc_clk_hz(void);
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const unsigned int cm_get_f2s_per_ref_clk_hz(void);
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const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
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const unsigned int cm_get_intosc_clk_hz(void);
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const unsigned int cm_get_fpga_clk_hz(void);
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#define CLKMGR_EOSC1_HZ 25000000
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#define CLKMGR_INTOSC_HZ 460000000
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#define CLKMGR_FPGA_CLK_HZ 50000000
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/* Clock configuration accessors */
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const struct cm_config * const cm_get_default_config(void);
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struct cm_config {
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/* main group */
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u32 main_pll_mpuclk;
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u32 main_pll_nocclk;
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u32 main_pll_cntr2clk;
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u32 main_pll_cntr3clk;
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u32 main_pll_cntr4clk;
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u32 main_pll_cntr5clk;
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u32 main_pll_cntr6clk;
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u32 main_pll_cntr7clk;
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u32 main_pll_cntr8clk;
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u32 main_pll_cntr9clk;
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u32 main_pll_nocdiv;
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u32 main_pll_pllglob;
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u32 main_pll_fdbck;
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u32 main_pll_pllc0;
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u32 main_pll_pllc1;
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u32 spare;
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/* peripheral group */
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u32 per_pll_cntr2clk;
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u32 per_pll_cntr3clk;
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u32 per_pll_cntr4clk;
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u32 per_pll_cntr5clk;
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u32 per_pll_cntr6clk;
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u32 per_pll_cntr7clk;
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u32 per_pll_cntr8clk;
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u32 per_pll_cntr9clk;
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u32 per_pll_emacctl;
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u32 per_pll_gpiodiv;
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u32 per_pll_pllglob;
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u32 per_pll_fdbck;
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u32 per_pll_pllc0;
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u32 per_pll_pllc1;
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/* incoming clock */
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u32 hps_osc_clk_hz;
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u32 fpga_clk_hz;
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};
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void cm_basic_init(const struct cm_config * const cfg);
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struct socfpga_clock_manager_main_pll {
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u32 en;
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u32 ens;
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u32 enr;
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u32 bypass;
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u32 bypasss;
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u32 bypassr;
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u32 mpuclk;
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u32 nocclk;
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u32 cntr2clk;
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u32 cntr3clk;
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u32 cntr4clk;
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u32 cntr5clk;
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u32 cntr6clk;
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u32 cntr7clk;
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u32 cntr8clk;
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u32 cntr9clk;
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u32 nocdiv;
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u32 pllglob;
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u32 fdbck;
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u32 mem;
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u32 memstat;
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u32 pllc0;
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u32 pllc1;
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u32 vcocalib;
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u32 _pad_0x90_0xA0[5];
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};
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struct socfpga_clock_manager_per_pll {
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u32 en;
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u32 ens;
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u32 enr;
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u32 bypass;
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u32 bypasss;
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u32 bypassr;
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u32 cntr2clk;
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u32 cntr3clk;
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u32 cntr4clk;
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u32 cntr5clk;
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u32 cntr6clk;
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u32 cntr7clk;
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u32 cntr8clk;
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u32 cntr9clk;
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u32 emacctl;
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u32 gpiodiv;
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u32 pllglob;
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u32 fdbck;
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u32 mem;
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u32 memstat;
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u32 pllc0;
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u32 pllc1;
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u32 vcocalib;
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u32 _pad_0x100_0x124[10];
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};
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struct socfpga_clock_manager {
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u32 ctrl;
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u32 stat;
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u32 testioctrl;
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u32 intrgen;
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u32 intrmsk;
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u32 intrclr;
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u32 intrsts;
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u32 intrstk;
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u32 intrraw;
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u32 _pad_0x24_0x2c[3];
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struct socfpga_clock_manager_main_pll main_pll;
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struct socfpga_clock_manager_per_pll per_pll;
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};
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#define CLKMGR_CTRL_SAFEMODE BIT(0)
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#define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007
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#define CLKMGR_BYPASS_PERPLL_ALL 0x0000007f
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#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001
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#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002
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#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004
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#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008
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#define CLKMGR_STAT_BUSY BIT(0)
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#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8)
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#define CLKMGR_STAT_PERPLL_LOCKED BIT(9)
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#define CLKMGR_PLLGLOB_PD_MASK 0x00000001
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#define CLKMGR_PLLGLOB_RST_MASK 0x00000002
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#define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0X3
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#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16
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#define CLKMGR_VCO_PSRC_EOSC1 0
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#define CLKMGR_VCO_PSRC_INTOSC 1
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#define CLKMGR_VCO_PSRC_F2S 2
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#define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0X3f
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#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8
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#define CLKMGR_CLKSRC_MASK 0x7
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#define CLKMGR_CLKSRC_OFFSET 16
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#define CLKMGR_CLKSRC_MAIN 0
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#define CLKMGR_CLKSRC_PER 1
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#define CLKMGR_CLKSRC_OSC1 2
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#define CLKMGR_CLKSRC_INTOSC 3
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#define CLKMGR_CLKSRC_FPGA 4
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#define CLKMGR_CLKCNT_MSK 0x7ff
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#define CLKMGR_FDBCK_MDIV_MASK 0xff
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#define CLKMGR_FDBCK_MDIV_OFFSET 24
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#define CLKMGR_PLLC0_DIV_MASK 0xff
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#define CLKMGR_PLLC1_DIV_MASK 0xff
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#define CLKMGR_PLLC0_EN_OFFSET 27
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#define CLKMGR_PLLC1_EN_OFFSET 24
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#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0
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#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8
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#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16
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#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24
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#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26
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#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28
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#define CLKMGR_NOCDIV_L4SPCLK_MASK 0X3
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#define CLKMGR_NOCDIV_DIV1 0
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#define CLKMGR_NOCDIV_DIV2 1
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#define CLKMGR_NOCDIV_DIV4 2
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#define CLKMGR_NOCDIV_DIV8 3
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#define CLKMGR_CSPDBGCLK_DIV1 0
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#define CLKMGR_CSPDBGCLK_DIV4 1
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#define CLKMGR_MSCNT_CONST 200
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#define CLKMGR_MDIV_CONST 6
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#define CLKMGR_HSCNT_CONST 9
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#define CLKMGR_VCOCALIB_MSCNT_MASK 0xff
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#define CLKMGR_VCOCALIB_MSCNT_OFFSET 9
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#define CLKMGR_VCOCALIB_HSCNT_MASK 0xff
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#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET 26
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#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET 27
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#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET 28
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#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020
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#endif /* _CLOCK_MANAGER_S10_ */
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