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https://github.com/brain-hackers/u-boot-brain
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a6bb0084c2
p2771-0000 has a couple of PCIe ports; one physically x4 desktop PCI connector (which may run at x2 electrically, depending on the board version and configuration) and a x1 connection to the M.2 slot (which may not be active, depending on the board version and configuration). This change enables those. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
42 lines
838 B
C
42 lines
838 B
C
/*
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* Copyright (c) 2013-2016, NVIDIA CORPORATION.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _P2771_0000_H
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#define _P2771_0000_H
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#include <linux/sizes.h>
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#include "tegra186-common.h"
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/* High-level configuration options */
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#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000"
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/* I2C */
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#define CONFIG_SYS_I2C_TEGRA
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/* SD/MMC */
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_TEGRA_MMC
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/* Environment in eMMC, at the end of 2nd "boot sector" */
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_SYS_MMC_ENV_PART 2
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#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
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/* PCI host support */
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#define CONFIG_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_CMD_PCI
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#include "tegra-common-post.h"
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/* Crystal is 38.4MHz. clk_m runs at half that rate */
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#define COUNTER_FREQUENCY 19200000
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#endif
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