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https://github.com/brain-hackers/u-boot-brain
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1fdcc8dfc7
Instead of using multiple macros, a data structure is used to pass board-specific parameters to MMDC DDR driver. Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
101 lines
2.5 KiB
C
101 lines
2.5 KiB
C
/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __LS1012ARDB_H__
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#define __LS1012ARDB_H__
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#include "ls1012a_common.h"
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/* DDR */
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 1
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#define CONFIG_NR_DRAM_BANKS 2
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#define CONFIG_SYS_SDRAM_SIZE 0x40000000
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#define CONFIG_CMD_MEMINFO
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#define CONFIG_CMD_MEMTEST
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#define CONFIG_SYS_MEMTEST_START 0x80000000
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#define CONFIG_SYS_MEMTEST_END 0x9fffffff
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/*
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* USB
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*/
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#define CONFIG_HAS_FSL_XHCI_USB
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#ifdef CONFIG_HAS_FSL_XHCI_USB
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#define CONFIG_USB_XHCI_FSL
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
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#endif
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/*
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* I2C IO expander
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*/
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#define I2C_MUX_IO1_ADDR 0x24
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#define __SW_BOOT_MASK 0xFC
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#define __SW_BOOT_EMU 0x10
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#define __SW_BOOT_BANK1 0x00
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#define __SW_BOOT_BANK2 0x01
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#define __SW_REV_MASK 0x07
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#define __SW_REV_A 0xF8
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#define __SW_REV_B 0xF0
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/* MMC */
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#define CONFIG_MMC
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#ifdef CONFIG_MMC
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
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#define CONFIG_GENERIC_MMC
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#define CONFIG_DOS_PARTITION
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#endif
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/* SATA */
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#define CONFIG_LIBATA
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#define CONFIG_SCSI
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#define CONFIG_SCSI_AHCI
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#define CONFIG_SCSI_AHCI_PLAT
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#define CONFIG_CMD_SCSI
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#define CONFIG_DOS_PARTITION
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_SYS_SATA AHCI_BASE_ADDR
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
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#define CONFIG_SYS_SCSI_MAX_LUN 1
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#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
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CONFIG_SYS_SCSI_MAX_LUN)
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#define CONFIG_PCI /* Enable PCI/PCIE */
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#define CONFIG_PCIE1 /* PCIE controller 1 */
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#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
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#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
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#define CONFIG_SYS_PCI_64BIT
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#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
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#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
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#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
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#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
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#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
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#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
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#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
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#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
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#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
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#define CONFIG_NET_MULTI
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#define CONFIG_PCI_PNP
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_MEMINFO
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#define CONFIG_CMD_MEMTEST
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#define CONFIG_SYS_MEMTEST_START 0x80000000
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#define CONFIG_SYS_MEMTEST_END 0x9fffffff
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#endif /* __LS1012ARDB_H__ */
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