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https://github.com/brain-hackers/u-boot-brain
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Add i.MX8QM ROM 7720a1 board support Boot log as below: U-Boot 2019.10-rc3-00004-gd073e0242f (Sep 20 2019 - 08:24:13 +0200) CPU: NXP i.MX8QM RevB A53 at 1200 MHz Model: Advantech iMX8QM Qseven series Board: ROM-7720-A1 4GB Build: SCFW 65afe5f6 Boot: SD2 DRAM: 4 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 Net: eth0: ethernet@5b040000Could not get PHY for FEC1: addr 1 , eth-1: ethernet@5b050000 Hit any key to stop autoboot: 0 Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
142 lines
2.9 KiB
C
142 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017-2018 NXP
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* Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
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*/
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#include <common.h>
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#include <errno.h>
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#include <linux/libfdt.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sci/sci.h>
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#include <asm/arch/imx8-pins.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
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(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
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(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
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(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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static iomux_cfg_t uart0_pads[] = {
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SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
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}
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int board_early_init_f(void)
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{
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sc_pm_clock_rate_t rate = SC_80MHZ;
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int ret;
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/* Set UART0 clock root to 80 MHz */
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ret = sc_pm_setup_uart(SC_R_UART_0, rate);
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if (ret)
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return ret;
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setup_iomux_uart();
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/* This is needed to because Kernel do not Power Up DC_0 */
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sc_pm_set_resource_power_mode(-1, SC_R_DC_0, SC_PM_PW_MODE_ON);
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sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON);
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return 0;
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}
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#if IS_ENABLED(CONFIG_FEC_MXC)
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#include <miiphy.h>
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int board_phy_config(struct phy_device *phydev)
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{
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#ifdef CONFIG_FEC_ENABLE_MAX7322
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u8 value;
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/* This is needed to drive the pads to 1.8V instead of 1.5V */
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i2c_set_bus_num(CONFIG_MAX7322_I2C_BUS);
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if (!i2c_probe(CONFIG_MAX7322_I2C_ADDR)) {
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/* Write 0x1 to enable O0 output, this device has no addr */
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/* hence addr length is 0 */
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value = 0x1;
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if (dm_i2c_write(CONFIG_MAX7322_I2C_ADDR, 0, 0, &value, 1))
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printf("MAX7322 write failed\n");
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} else {
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printf("MAX7322 Not found\n");
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}
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mdelay(1);
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#endif
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int checkboard(void)
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{
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puts("Board: ROM-7720-A1 4GB\n");
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build_info();
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print_bootinfo();
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return 0;
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}
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int board_init(void)
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{
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/* Power up base board */
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sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON);
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return 0;
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}
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void detail_board_ddr_info(void)
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{
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puts("\nDDR ");
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}
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/*
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* Board specific reset that is system reset.
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*/
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void reset_cpu(ulong addr)
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{
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/* TODO */
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}
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int board_mmc_get_env_dev(int devno)
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{
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return devno;
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}
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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env_set("board_name", "ROM-7720-A1");
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env_set("board_rev", "iMX8QM");
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#endif
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env_set("sec_boot", "no");
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#ifdef CONFIG_AHAB_BOOT
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env_set("sec_boot", "yes");
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#endif
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return 0;
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}
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