mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-25 20:39:43 +09:00
3ab019e1dc
To fix the build error when build for Altera dev kit, not virtual target. At same time, set the build for Altera dev kit as default instead virtual target. With that, U-Boot is booting well and SPL still lack of few drivers. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
144 lines
4.3 KiB
C
144 lines
4.3 KiB
C
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/u-boot.h>
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#include <asm/utils.h>
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#include <version.h>
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#include <image.h>
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#include <asm/arch/reset_manager.h>
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#include <spl.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/freeze_controller.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/scan_manager.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_RAM;
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}
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/*
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* Board initialization after bss clearance
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*/
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void spl_board_init(void)
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{
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#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
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cm_config_t cm_default_cfg = {
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/* main group */
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MAIN_VCO_BASE,
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CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
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CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
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CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
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CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
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CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
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CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
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CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
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CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
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CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
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CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
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CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
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CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
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CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
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CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) |
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CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
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CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) |
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CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
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CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) |
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CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
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CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
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CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
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CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) |
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CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
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CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
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CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
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CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
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CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
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CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) |
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CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
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CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
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/* peripheral group */
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PERI_VCO_BASE,
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CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
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CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
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CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
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CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
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CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
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CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
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CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
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CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
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CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
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CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
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CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
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CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
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CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
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CONFIG_HPS_PERPLLGRP_DIV_USBCLK) |
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CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
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CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) |
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CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
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CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) |
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CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
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CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
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CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
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CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
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CLKMGR_PERPLLGRP_SRC_QSPI_SET(
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CONFIG_HPS_PERPLLGRP_SRC_QSPI) |
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CLKMGR_PERPLLGRP_SRC_NAND_SET(
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CONFIG_HPS_PERPLLGRP_SRC_NAND) |
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CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
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CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
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/* sdram pll group */
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SDR_VCO_BASE,
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CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
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CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) |
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CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
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CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
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CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
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CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) |
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CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
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CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
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CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
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CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) |
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CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
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CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
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CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
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CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
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CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
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CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
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};
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debug("Freezing all I/O banks\n");
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/* freeze all IO banks */
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sys_mgr_frzctrl_freeze_req();
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debug("Reconfigure Clock Manager\n");
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/* reconfigure the PLLs */
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cm_basic_init(&cm_default_cfg);
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/* configure the IOCSR / IO buffer settings */
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if (scan_mgr_configure_iocsr())
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hang();
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/* configure the pin muxing through system manager */
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sysmgr_pinmux_init();
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#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
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/* de-assert reset for peripherals and bridges based on handoff */
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reset_deassert_peripherals_handoff();
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debug("Unfreezing/Thaw all I/O banks\n");
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/* unfreeze / thaw all IO banks */
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sys_mgr_frzctrl_thaw_req();
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/* enable console uart printing */
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preloader_console_init();
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}
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