Simon Glass 191c008a21 x86: Implement a cache for Memory Reference Code parameters ... The memory reference code takes a very long time to 'train' its SDRAM interface, around half a second. To avoid this delay on every boot we can store the parameters from the last training sessions to speed up the next. Add an implementation of this, storing the training data in CMOS RAM and SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org>		2015-01-24 06:13:45 -07:00
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bd82x6x.h	x86: Add initial video device init for Intel GMA	2014-11-25 07:11:16 -07:00
gpio.h	x86: ich6-gpio: Move setup_pch_gpios() to board support codes	2014-12-13 22:32:04 -07:00
me.h	x86: ivybridge: Implement SDRAM init	2014-11-21 07:34:15 +01:00
microcode.h	x86: ivybridge: Update microcode early in boot	2015-01-13 07:25:02 -08:00
model_206ax.h	x86: ivybridge: Add northbridge init functions	2014-11-25 06:34:14 -07:00
mrccache.h	x86: Implement a cache for Memory Reference Code parameters	2015-01-24 06:13:45 -07:00
pch.h	x86: ivybridge: Add SATA init	2014-11-25 06:34:01 -07:00
pei_data.h	x86: move arch-specific asmlinkage to <asm/linkage.h>	2014-12-15 07:22:53 -07:00
sandybridge.h	x86: ivybridge: Add northbridge init functions	2014-11-25 06:34:14 -07:00