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ee8b1e2959
u-boot-brain/arch/mips/cpu/mips32
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Gabor Juhos ee8b1e2959 MIPS: mips32/cache.S: store cache line size in t8 register 
Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:07 -04:00
..
au1x00 Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
incaip Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
cache.S MIPS: mips32/cache.S: store cache line size in t8 register 2013-07-24 09:51:07 -04:00
config.mk Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
cpu.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
interrupts.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
Makefile Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
start.S MIPS: mips32/start.S: rework relocation info check 2013-07-24 09:51:05 -04:00
time.c MIPS: mips32/time.c: fix checkpatch errors/warnings 2013-07-24 09:51:04 -04:00