mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 05:06:16 +09:00
3f786bb854
call to reset PHY chip. Current PHY Software Reset operation in guruplug does not poll reset bit in control register to go to 0(auto clearing) for making sure reset was successful.This patch uses standard miiphy call miiphy_reset to make sure proper PHY reset operation. Signed-off-by: Mahavir Jain <mjain@marvell.com>
161 lines
3.6 KiB
C
161 lines
3.6 KiB
C
/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Siddarth Gore <gores@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <asm/arch/kirkwood.h>
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#include <asm/arch/mpp.h>
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#include "guruplug.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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/*
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* default gpio configuration
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(GURUPLUG_OE_VAL_LOW,
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GURUPLUG_OE_VAL_HIGH,
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GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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u32 kwmpp_config[] = {
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MPP0_NF_IO2,
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MPP1_NF_IO3,
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MPP2_NF_IO4,
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MPP3_NF_IO5,
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP6_SYSRST_OUTn,
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MPP7_GPO, /* GPIO_RST */
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MPP8_TW_SDA,
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MPP9_TW_SCK,
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP12_SD_CLK,
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MPP13_SD_CMD,
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MPP14_SD_D0,
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MPP15_SD_D1,
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MPP16_SD_D2,
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MPP17_SD_D3,
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MPP18_NF_IO0,
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MPP19_NF_IO1,
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MPP20_GE1_0,
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MPP21_GE1_1,
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MPP22_GE1_2,
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MPP23_GE1_3,
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MPP24_GE1_4,
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MPP25_GE1_5,
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MPP26_GE1_6,
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MPP27_GE1_7,
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MPP28_GE1_8,
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MPP29_GE1_9,
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MPP30_GE1_10,
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MPP31_GE1_11,
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MPP32_GE1_12,
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MPP33_GE1_13,
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MPP34_GE1_14,
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MPP35_GE1_15,
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MPP36_GPIO,
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MPP37_GPIO,
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MPP38_GPIO,
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MPP39_GPIO,
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MPP40_TDM_SPI_SCK,
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MPP41_TDM_SPI_MISO,
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MPP42_TDM_SPI_MOSI,
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MPP43_GPIO,
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MPP44_GPIO,
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MPP45_GPIO,
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MPP46_GPIO, /* M_RLED */
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MPP47_GPIO, /* M_GLED */
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MPP48_GPIO, /* B_RLED */
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MPP49_GPIO, /* B_GLED */
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0
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};
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kirkwood_mpp_conf(kwmpp_config);
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/*
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* arch number of board
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*/
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gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
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return 0;
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}
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int dram_init(void)
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{
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int i;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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gd->bd->bi_dram[i].start = kw_sdram_bar(i);
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gd->bd->bi_dram[i].size = kw_sdram_bs(i);
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}
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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void mv_phy_88e1121_init(char *name)
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{
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u16 reg;
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u16 devadr;
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if (miiphy_set_current_dev(name))
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return;
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/* command to read PHY dev address */
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if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
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printf("Err..%s could not read PHY dev address\n",
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__FUNCTION__);
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return;
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}
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2);
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miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, ®);
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reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL);
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miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg);
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miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
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/* reset the phy */
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miiphy_reset(name, devadr);
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printf("88E1121 Initialized on %s\n", name);
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}
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void reset_phy(void)
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{
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/* configure and initialize both PHY's */
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mv_phy_88e1121_init("egiga0");
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mv_phy_88e1121_init("egiga1");
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}
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#endif /* CONFIG_RESET_PHY_R */
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