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https://github.com/brain-hackers/u-boot-brain
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![Stefan Roese](/assets/img/avatar_default.png)
On MIPS platforms, mapping of the base address is needed. This patch switches from dev_get_addr() to dev_remap_addr() to get the mapped base address of the xHCI controller. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de>
194 lines
4.6 KiB
C
194 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* DWC3 controller driver
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*
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* Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <generic-phy.h>
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#include <log.h>
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#include <usb.h>
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#include <dwc3-uboot.h>
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#include <linux/delay.h>
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#include <usb/xhci.h>
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#include <asm/io.h>
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#include <linux/usb/dwc3.h>
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#include <linux/usb/otg.h>
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struct xhci_dwc3_platdata {
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struct phy_bulk phys;
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};
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void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
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{
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clrsetbits_le32(&dwc3_reg->g_ctl,
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DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
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DWC3_GCTL_PRTCAPDIR(mode));
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}
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static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
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{
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/* Assert USB3 PHY reset */
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setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
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/* Assert USB2 PHY reset */
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setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
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mdelay(100);
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/* Clear USB3 PHY reset */
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clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
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/* Clear USB2 PHY reset */
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clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
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}
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void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
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{
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/* Before Resetting PHY, put Core in Reset */
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setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
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/* reset USB3 phy - if required */
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dwc3_phy_reset(dwc3_reg);
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mdelay(100);
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/* After PHYs are stable we can take Core out of reset state */
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clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
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}
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int dwc3_core_init(struct dwc3 *dwc3_reg)
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{
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u32 reg;
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u32 revision;
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unsigned int dwc3_hwparams1;
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revision = readl(&dwc3_reg->g_snpsid);
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/* This should read as U3 followed by revision number */
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if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
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puts("this is not a DesignWare USB3 DRD Core\n");
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return -1;
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}
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dwc3_core_soft_reset(dwc3_reg);
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dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
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reg = readl(&dwc3_reg->g_ctl);
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reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
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reg &= ~DWC3_GCTL_DISSCRAMBLE;
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switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
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case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
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reg &= ~DWC3_GCTL_DSBLCLKGTNG;
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break;
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default:
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debug("No power optimization available\n");
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}
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/*
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* WORKAROUND: DWC3 revisions <1.90a have a bug
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* where the device can fail to connect at SuperSpeed
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* and falls back to high-speed mode which causes
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* the device to enter a Connect/Disconnect loop
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*/
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if ((revision & DWC3_REVISION_MASK) < 0x190a)
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reg |= DWC3_GCTL_U2RSTECN;
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writel(reg, &dwc3_reg->g_ctl);
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return 0;
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}
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void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
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{
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setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
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GFLADJ_30MHZ(val));
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}
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#if CONFIG_IS_ENABLED(DM_USB)
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static int xhci_dwc3_probe(struct udevice *dev)
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{
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struct xhci_hcor *hcor;
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struct xhci_hccr *hccr;
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struct dwc3 *dwc3_reg;
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enum usb_dr_mode dr_mode;
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struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
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const char *phy;
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u32 reg;
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int ret;
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hccr = (struct xhci_hccr *)((uintptr_t)dev_remap_addr(dev));
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hcor = (struct xhci_hcor *)((uintptr_t)hccr +
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HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
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ret = dwc3_setup_phy(dev, &plat->phys);
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if (ret && (ret != -ENOTSUPP))
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return ret;
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dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
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dwc3_core_init(dwc3_reg);
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/* Set dwc3 usb2 phy config */
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reg = readl(&dwc3_reg->g_usb2phycfg[0]);
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phy = dev_read_string(dev, "phy_type");
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if (phy && strcmp(phy, "utmi_wide") == 0) {
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reg |= DWC3_GUSB2PHYCFG_PHYIF;
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reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
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reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
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}
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if (dev_read_bool(dev, "snps,dis_enblslpm-quirk"))
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reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
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if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
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reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
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if (dev_read_bool(dev, "snps,dis_u2_susphy_quirk"))
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reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
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writel(reg, &dwc3_reg->g_usb2phycfg[0]);
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dr_mode = usb_get_dr_mode(dev->node);
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if (dr_mode == USB_DR_MODE_UNKNOWN)
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/* by default set dual role mode to HOST */
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dr_mode = USB_DR_MODE_HOST;
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dwc3_set_mode(dwc3_reg, dr_mode);
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return xhci_register(dev, hccr, hcor);
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}
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static int xhci_dwc3_remove(struct udevice *dev)
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{
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struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
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dwc3_shutdown_phy(dev, &plat->phys);
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return xhci_deregister(dev);
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}
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static const struct udevice_id xhci_dwc3_ids[] = {
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{ .compatible = "snps,dwc3" },
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{ }
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};
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U_BOOT_DRIVER(xhci_dwc3) = {
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.name = "xhci-dwc3",
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.id = UCLASS_USB,
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.of_match = xhci_dwc3_ids,
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.probe = xhci_dwc3_probe,
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.remove = xhci_dwc3_remove,
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.ops = &xhci_usb_ops,
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.priv_auto_alloc_size = sizeof(struct xhci_ctrl),
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.platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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#endif
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