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https://github.com/brain-hackers/u-boot-brain
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509d4b9545
Xilinx ATF extending options for passing images from BL2(FSBL) to BL31. U-Boot SPL is FSBL replacement that's why it should generate handoff structure the same. Support only one entry which is U-Boot in EL2 itself. When FIT image is adopted structure generate should be data driven. Currently ATF is placing this structure at the beggining of OCM which is rewriting early parts of ATF which should be unused at that time. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
27 lines
525 B
C
27 lines
525 B
C
/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_SYS_PROTO_H
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#define _ASM_ARCH_SYS_PROTO_H
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#ifndef CONFIG_CLK_ZYNQMP
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/* Setup clk for network */
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static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
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{
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}
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#endif
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int zynq_slcr_get_mio_pin_status(const char *periph);
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unsigned int zynqmp_get_silicon_version(void);
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void psu_init(void);
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void handoff_setup(void);
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#endif /* _ASM_ARCH_SYS_PROTO_H */
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