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https://github.com/brain-hackers/u-boot-brain
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c5b34a29ac
Set Seaboard to optimal memory settings based on the SOC in use (T20 or T25). Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/ap20.h>
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#include <asm/arch/clk_rst.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/emc.h>
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#include <asm/arch/pmu.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/tegra2.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* These rates are hard-coded for now, until fdt provides them */
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#define EMC_SDRAM_RATE_T20 (333000 * 2 * 1000)
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#define EMC_SDRAM_RATE_T25 (380000 * 2 * 1000)
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int board_emc_init(void)
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{
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unsigned rate;
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switch (tegra_get_chip_type()) {
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default:
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case TEGRA_SOC_T20:
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rate = EMC_SDRAM_RATE_T20;
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break;
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case TEGRA_SOC_T25:
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rate = EMC_SDRAM_RATE_T25;
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break;
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}
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return tegra_set_emc(gd->fdt_blob, rate);
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}
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