mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
154 lines
4.1 KiB
C
154 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/fsl_serdes.h>
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#include <asm/immap_85xx.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <malloc.h>
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#include <fsl_dtsec.h>
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#include <vsc9953.h>
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#include "../common/fman.h"
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_FMAN_ENET
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struct memac_mdio_info memac_mdio_info;
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unsigned int i;
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int phy_addr = 0;
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#ifdef CONFIG_VSC9953
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phy_interface_t phy_int;
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struct mii_dev *bus;
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#endif
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printf("Initializing Fman\n");
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memac_mdio_info.regs =
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(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
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memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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/* Register the real 1G MDIO bus */
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fm_memac_mdio_init(bis, &memac_mdio_info);
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/*
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* Program on board RGMII, SGMII PHY addresses.
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*/
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for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
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int idx = i - FM1_DTSEC1;
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switch (fm_info_get_enet_if(i)) {
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#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
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case PHY_INTERFACE_MODE_SGMII:
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/* T1040RDB & T1040D4RDB only supports SGMII on
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* DTSEC3
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*/
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fm_info_set_phy_address(FM1_DTSEC3,
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CONFIG_SYS_SGMII1_PHY_ADDR);
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break;
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#endif
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#ifdef CONFIG_TARGET_T1042RDB
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case PHY_INTERFACE_MODE_SGMII:
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/* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
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if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
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fm_info_set_phy_address(i, 0);
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/* T1042RDB only supports SGMII on DTSEC3 */
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fm_info_set_phy_address(FM1_DTSEC3,
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CONFIG_SYS_SGMII1_PHY_ADDR);
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break;
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#endif
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#ifdef CONFIG_TARGET_T1042D4RDB
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case PHY_INTERFACE_MODE_SGMII:
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/* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
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* & DTSEC3
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*/
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if (FM1_DTSEC1 == i)
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phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR;
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if (FM1_DTSEC2 == i)
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phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR;
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if (FM1_DTSEC3 == i)
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phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR;
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fm_info_set_phy_address(i, phy_addr);
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break;
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#endif
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case PHY_INTERFACE_MODE_RGMII:
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if (FM1_DTSEC4 == i)
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phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
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if (FM1_DTSEC5 == i)
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phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
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fm_info_set_phy_address(i, phy_addr);
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break;
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case PHY_INTERFACE_MODE_QSGMII:
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fm_info_set_phy_address(i, 0);
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break;
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case PHY_INTERFACE_MODE_NONE:
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fm_info_set_phy_address(i, 0);
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break;
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default:
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printf("Fman1: DTSEC%u set to unknown interface %i\n",
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idx + 1, fm_info_get_enet_if(i));
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fm_info_set_phy_address(i, 0);
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break;
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}
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if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
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fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE)
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fm_info_set_mdio(i, NULL);
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else
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fm_info_set_mdio(i,
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miiphy_get_dev_by_name(
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DEFAULT_FM_MDIO_NAME));
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}
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#ifdef CONFIG_VSC9953
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/* SerDes configured for QSGMII */
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if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
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for (i = 0; i < 4; i++) {
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bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
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phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
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phy_int = PHY_INTERFACE_MODE_QSGMII;
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vsc9953_port_info_set_mdio(i, bus);
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vsc9953_port_info_set_phy_address(i, phy_addr);
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vsc9953_port_info_set_phy_int(i, phy_int);
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vsc9953_port_enable(i);
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}
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}
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if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
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for (i = 4; i < 8; i++) {
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bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
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phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
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phy_int = PHY_INTERFACE_MODE_QSGMII;
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vsc9953_port_info_set_mdio(i, bus);
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vsc9953_port_info_set_phy_address(i, phy_addr);
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vsc9953_port_info_set_phy_int(i, phy_int);
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vsc9953_port_enable(i);
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}
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}
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/* Connect DTSEC1 to L2 switch if it doesn't have a PHY */
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if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0)
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vsc9953_port_enable(8);
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/* Connect DTSEC2 to L2 switch if it doesn't have a PHY */
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if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
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/* Enable L2 On MAC2 using SCFG */
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)
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CONFIG_SYS_MPC85xx_SCFG;
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out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
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(0x80000000));
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vsc9953_port_enable(9);
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}
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#endif
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cpu_eth_init(bis);
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#endif
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return pci_eth_init(bis);
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}
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