mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 05:06:16 +09:00
92b50ffef9
The environment is the canonical storage location of the mac address, so we're killing off the global data location and moving everything to querying the env directly. Also rename load_sernum_ethaddr() to misc_init_r() so we don't need to handle this board specially in common ARM code. Signed-off-by: Mike Frysinger <vapier@gentoo.org> CC: Ben Warren <biggerbadderben@gmail.com>
238 lines
8.3 KiB
C
238 lines
8.3 KiB
C
/*
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* 2004-2005 Gary Jennejohn <garyj@denx.de>
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*
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* Configuration settings for the CMC PU2 board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* ARM asynchronous clock */
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#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
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#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */
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#define AT91_SLOW_CLOCK 32768 /* slow clock */
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#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
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#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
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#define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define USE_920T_MMU 1
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
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/* flash */
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#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
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#define CONFIG_SYS_MC_PUP_VAL 0x00000000
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#define CONFIG_SYS_MC_PUER_VAL 0x00000000
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#define CONFIG_SYS_MC_ASR_VAL 0x00000000
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#define CONFIG_SYS_MC_AASR_VAL 0x00000000
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#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
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#define CONFIG_SYS_SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
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/* clocks */
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#define CONFIG_SYS_PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */
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#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
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#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
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/* sdram */
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#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
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#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
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#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
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#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
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#define CONFIG_SYS_SDRC_CR_VAL 0x3399c1d4 /* set up the CONFIG_SYS_SDRAM */
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#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
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#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
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#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
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#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
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#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
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#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
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#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
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#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
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#else
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#define CONFIG_SKIP_RELOCATE_UBOOT
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CONFIG_BAUDRATE 9600
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/*
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* Hardware drivers
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*/
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/* define one of these to choose the DBGU, USART0 or USART1 as console */
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#undef CONFIG_DBGU
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#define CONFIG_USART0
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#undef CONFIG_USART1
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#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
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#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
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#define CONFIG_HARD_I2C
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#ifdef CONFIG_HARD_I2C
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#define CONFIG_SYS_I2C_SPEED 0 /* not used */
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#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
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#define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x32
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
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#else
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#define CONFIG_TIMESTAMP
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#endif
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/* still about 20 kB free with this defined */
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_BOOTDELAY 1
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_SNTP
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_MISC
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#if defined(CONFIG_HARD_I2C)
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_I2C
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#endif
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#define CONFIG_MISC_INIT_R
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#define CONFIG_SYS_LONGHELP
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#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
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#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x20000000
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#define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
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#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
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#define CONFIG_DRIVER_ETHER
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_AT91C_USE_RMII
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#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
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#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
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#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
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#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
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#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
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#define PHYS_FLASH_1 0x10000000
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#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_FLASH_ERASE_TOUT (11 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
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#define CONFIG_SYS_FLASH_WRITE_TOUT ( 2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_OFFSET 0x20000 /* after u-boot.bin */
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#define CONFIG_ENV_SECT_SIZE (64 << 10) /* sectors are 64 kB */
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#define CONFIG_ENV_SIZE (16 << 10) /* Use only 16 kB */
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#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */
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/* AT91C_TC_TIMER_DIV1_CLOCK */
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#define CONFIG_STACKSIZE (32*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#error CONFIG_USE_IRQ not supported
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \
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"addmtd;bootm\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"net_cramfs=tftp ${loadaddr} ${bootfile}; run flashargs addip " \
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"addcons addmtd; bootm\0" \
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"flash_cramfs=run flashargs addip addcons addmtd; bootm 10030000\0" \
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"flashargs=setenv bootargs root=/dev/mtdblock3 ro\0" \
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"addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
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"${hostname}::off\0" \
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"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
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"addmtd=setenv bootargs ${bootargs} mtdparts=cmc_pu2:128k(uboot)ro," \
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"64k(environment),768k(linux),4096k(root),-\0" \
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"load=tftp ${loadaddr} ${loadfile}\0" \
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"update=protect off 10000000 1001ffff;erase 10000000 1001ffff; " \
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"cp.b ${loadaddr} 10000000 ${filesize};" \
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"protect on 10000000 1001ffff\0" \
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"updatel=era 10030000 100effff;tftp ${loadaddr} ${bootfile}; " \
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"cp.b ${loadaddr} 10030000 ${filesize}\0" \
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"updatec=era 100f0000 104effff;tftp ${loadaddr} ${cramfsimage}; " \
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"cp.b ${loadaddr} 100f0000 ${filesize}\0" \
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"updatej=era 104f0000 107fffff;tftp ${loadaddr} ${jffsimage}; " \
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"cp.b ${loadaddr} 104f0000 ${filesize}\0" \
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"cramfsimage=cramfs_cmc-pu2.img\0" \
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"jffsimage=jffs2_cmc-pu2.img\0" \
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"loadfile=u-boot_cmc-pu2.bin\0" \
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"bootfile=uImage_cmc-pu2\0" \
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"loadaddr=0x20800000\0" \
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"hostname=CMC-TC-PU2\0" \
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"bootcmd=run dhcp_start;run flash_cramfs\0" \
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"autoload=n\0" \
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"dhcp_start=echo no DHCP\0" \
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"ipaddr=192.168.0.190\0"
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#endif /* __CONFIG_H */
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