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![Wolfgang Denk](/assets/img/avatar_default.png)
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
177 lines
3.6 KiB
C
177 lines
3.6 KiB
C
/*
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* Copyright (C) 2012 Linaro Limited
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* Mathieu Poirier <mathieu.poirier@linaro.org>
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*
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* Based on original code from Joakim Axelsson at ST-Ericsson
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* (C) Copyright 2010 ST-Ericsson
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/prcmu.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/hardware.h>
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#define CPUID_DB8500V1 0x411fc091
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#define CPUID_DB8500V2 0x412fc091
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#define ASICID_DB8500V11 0x008500A1
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#define CACHE_CONTR_BASE 0xA0412000
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/* Cache controller register offsets
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* as found in ARM's technical reference manual
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*/
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#define CACHE_INVAL_BY_WAY (CACHE_CONTR_BASE + 0x77C)
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#define CACHE_LOCKDOWN_BY_D (CACHE_CONTR_BASE + 0X900)
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#define CACHE_LOCKDOWN_BY_I (CACHE_CONTR_BASE + 0X904)
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static unsigned int read_asicid(void);
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static inline unsigned int read_cpuid(void)
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{
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unsigned int val;
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/* Main ID register (MIDR) */
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asm("mrc p15, 0, %0, c0, c0, 0"
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: "=r" (val)
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:
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: "cc");
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return val;
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}
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static int cpu_is_u8500v11(void)
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{
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return read_asicid() == ASICID_DB8500V11;
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}
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static int cpu_is_u8500v2(void)
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{
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return read_cpuid() == CPUID_DB8500V2;
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}
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static unsigned int read_asicid(void)
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{
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unsigned int *address;
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if (cpu_is_u8500v2())
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address = (void *) U8500_ASIC_ID_LOC_V2;
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else
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address = (void *) U8500_ASIC_ID_LOC_ED_V1;
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return readl(address);
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}
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void cpu_cache_initialization(void)
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{
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unsigned int value;
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/* invalidate all cache entries */
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writel(0xFFFF, CACHE_INVAL_BY_WAY);
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/* ways are set to '0' when they are totally
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* cleaned and invalidated
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*/
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do {
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value = readl(CACHE_INVAL_BY_WAY);
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} while (value & 0xFF);
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/* Invalidate register 9 D and I lockdown */
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writel(0xFF, CACHE_LOCKDOWN_BY_D);
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writel(0xFF, CACHE_LOCKDOWN_BY_I);
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}
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#ifdef CONFIG_ARCH_CPU_INIT
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/*
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* SOC specific cpu init
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*/
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int arch_cpu_init(void)
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{
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db8500_prcmu_init();
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db8500_clocks_init();
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return 0;
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}
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#endif /* CONFIG_ARCH_CPU_INIT */
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#ifdef CONFIG_MMC
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int u8500_mmc_power_init(void)
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{
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int ret;
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int enable, voltage;
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int ab8500_revision;
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if (!cpu_is_u8500v11() && !cpu_is_u8500v2())
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return 0;
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/* Get AB8500 revision */
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ret = ab8500_read(AB8500_MISC, AB8500_REV_REG);
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if (ret < 0)
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goto out;
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ab8500_revision = ret;
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/*
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* On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD
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* card to work. This is done by enabling the regulators in the AB8500
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* via PRCMU I2C transactions.
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*
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* This code is derived from the handling of AB8500_LDO_VAUX3 in
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* ab8500_ldo_enable() and ab8500_ldo_disable() in Linux.
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*
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* Turn off and delay is required to have it work across soft reboots.
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*/
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/* Turn off (read-modify-write) */
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ret = ab8500_read(AB8500_REGU_CTRL2,
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AB8500_REGU_VRF1VAUX3_REGU_REG);
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if (ret < 0)
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goto out;
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enable = ret;
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/* Turn off */
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ret = ab8500_write(AB8500_REGU_CTRL2,
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AB8500_REGU_VRF1VAUX3_REGU_REG,
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enable & ~LDO_VAUX3_ENABLE_MASK);
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if (ret < 0)
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goto out;
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udelay(10 * 1000);
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/* Set the voltage to 2.91 V or 2.9 V without overriding VRF1 value */
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ret = ab8500_read(AB8500_REGU_CTRL2,
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AB8500_REGU_VRF1VAUX3_SEL_REG);
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if (ret < 0)
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goto out;
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voltage = ret;
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if (ab8500_revision < 0x20) {
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voltage &= ~LDO_VAUX3_SEL_MASK;
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voltage |= LDO_VAUX3_SEL_2V9;
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} else {
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voltage &= ~LDO_VAUX3_V2_SEL_MASK;
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voltage |= LDO_VAUX3_V2_SEL_2V91;
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}
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ret = ab8500_write(AB8500_REGU_CTRL2,
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AB8500_REGU_VRF1VAUX3_SEL_REG, voltage);
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if (ret < 0)
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goto out;
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/* Turn on the supply */
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enable &= ~LDO_VAUX3_ENABLE_MASK;
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enable |= LDO_VAUX3_ENABLE_VAL;
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ret = ab8500_write(AB8500_REGU_CTRL2,
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AB8500_REGU_VRF1VAUX3_REGU_REG, enable);
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out:
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return ret;
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}
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#endif /* CONFIG_MMC */
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