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https://github.com/brain-hackers/u-boot-brain
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![Wang Huan](/assets/img/avatar_default.png)
The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
137 lines
3.2 KiB
C
137 lines
3.2 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/arch/clock.h>
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#include <linux/ctype.h>
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#ifdef CONFIG_FSL_ESDHC
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#include <fsl_esdhc.h>
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#endif
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#include <tsec.h>
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DECLARE_GLOBAL_DATA_PTR;
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void ft_fixup_enet_phy_connect_type(void *fdt)
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{
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struct eth_device *dev;
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struct tsec_private *priv;
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const char *enet_path, *phy_path;
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char enet[16];
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char phy[16];
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int phy_node;
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int i = 0;
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int enet_id = 0;
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uint32_t ph;
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while ((dev = eth_get_dev_by_index(i++)) != NULL) {
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if (strstr(dev->name, "eTSEC1"))
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enet_id = 0;
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else if (strstr(dev->name, "eTSEC2"))
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enet_id = 1;
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else if (strstr(dev->name, "eTSEC3"))
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enet_id = 2;
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else
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continue;
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priv = dev->priv;
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if (priv->flags & TSEC_SGMII)
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continue;
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sprintf(enet, "ethernet%d", enet_id);
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enet_path = fdt_get_alias(fdt, enet);
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if (!enet_path)
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continue;
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sprintf(phy, "enet%d_rgmii_phy", enet_id);
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phy_path = fdt_get_alias(fdt, phy);
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if (!phy_path)
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continue;
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phy_node = fdt_path_offset(fdt, phy_path);
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if (phy_node < 0)
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continue;
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ph = fdt_create_phandle(fdt, phy_node);
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if (ph)
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do_fixup_by_path_u32(fdt, enet_path,
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"phy-handle", ph, 1);
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do_fixup_by_path(fdt, enet_path, "phy-connection-type",
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phy_string_for_interface(
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PHY_INTERFACE_MODE_RGMII_ID),
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sizeof(phy_string_for_interface(
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PHY_INTERFACE_MODE_RGMII_ID)),
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1);
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}
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}
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void ft_cpu_setup(void *blob, bd_t *bd)
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{
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int off;
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int val;
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const char *sysclk_path;
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unsigned long busclk = get_bus_freq(0);
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fdt_fixup_ethernet(blob);
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off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
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while (off != -FDT_ERR_NOTFOUND) {
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val = gd->cpu_clk;
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fdt_setprop(blob, off, "clock-frequency", &val, 4);
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off = fdt_node_offset_by_prop_value(blob, off,
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"device_type", "cpu", 4);
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}
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do_fixup_by_prop_u32(blob, "device_type", "soc",
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4, "bus-frequency", busclk / 2, 1);
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ft_fixup_enet_phy_connect_type(blob);
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#ifdef CONFIG_SYS_NS16550
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do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
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"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
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#endif
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sysclk_path = fdt_get_alias(blob, "sysclk");
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if (sysclk_path)
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do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
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CONFIG_SYS_CLK_FREQ, 1);
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do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
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"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
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#if defined(CONFIG_FSL_ESDHC)
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fdt_fixup_esdhc(blob, bd);
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#endif
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/*
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* platform bus clock = system bus clock/2
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* Here busclk = system bus clock
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* We are using the platform bus clock as 1588 Timer reference
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* clock source select
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*/
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do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
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"timer-frequency", busclk / 2, 1);
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/*
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* clock-freq should change to clock-frequency and
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* flexcan-v1.0 should change to p1010-flexcan respectively
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* in the future.
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*/
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do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
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"clock_freq", busclk / 2, 1);
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do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
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"clock-frequency", busclk / 2, 1);
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do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
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"clock-frequency", busclk / 2, 1);
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}
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