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![Michal Simek](/assets/img/avatar_default.png)
There is no reason to detect phy when core is doing it for us. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
773 lines
21 KiB
C
773 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2011 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* Based on Xilinx gmac driver:
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* (C) Copyright 2011 Xilinx
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <net.h>
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#include <netdev.h>
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#include <config.h>
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#include <console.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <phy.h>
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#include <miiphy.h>
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#include <wait_bit.h>
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#include <watchdog.h>
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#include <asm/system.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/errno.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Bit/mask specification */
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#define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
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#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
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#define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
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#define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
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#define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
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#define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
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#define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
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#define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
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#define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
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#define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
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#define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
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/* Wrap bit, last descriptor */
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#define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
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#define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
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#define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
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#define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
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#define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
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#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
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#define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
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#define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
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#define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
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#define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
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#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
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#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
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#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
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#ifdef CONFIG_ARM64
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#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
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#else
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#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
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#endif
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#ifdef CONFIG_ARM64
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# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
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#else
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# define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
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#endif
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#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
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ZYNQ_GEM_NWCFG_FDEN | \
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ZYNQ_GEM_NWCFG_FSREM | \
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ZYNQ_GEM_NWCFG_MDCCLKDIV)
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#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
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#define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
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/* Use full configured addressable space (8 Kb) */
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#define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
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/* Use full configured addressable space (4 Kb) */
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#define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
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/* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
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#define ZYNQ_GEM_DMACR_RXBUF 0x00180000
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#if defined(CONFIG_PHYS_64BIT)
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# define ZYNQ_GEM_DMA_BUS_WIDTH BIT(30) /* 64 bit bus */
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#else
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# define ZYNQ_GEM_DMA_BUS_WIDTH (0 << 30) /* 32 bit bus */
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#endif
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#define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
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ZYNQ_GEM_DMACR_RXSIZE | \
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ZYNQ_GEM_DMACR_TXSIZE | \
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ZYNQ_GEM_DMACR_RXBUF | \
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ZYNQ_GEM_DMA_BUS_WIDTH)
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#define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
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#define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
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#define ZYNQ_GEM_DCFG_DBG6_DMA_64B BIT(23)
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/* Use MII register 1 (MII status register) to detect PHY */
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#define PHY_DETECT_REG 1
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/* Mask used to verify certain PHY features (or register contents)
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* in the register above:
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* 0x1000: 10Mbps full duplex support
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* 0x0800: 10Mbps half duplex support
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* 0x0008: Auto-negotiation support
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*/
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#define PHY_DETECT_MASK 0x1808
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/* TX BD status masks */
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#define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
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#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
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#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
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/* Clock frequencies for different speeds */
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#define ZYNQ_GEM_FREQUENCY_10 2500000UL
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#define ZYNQ_GEM_FREQUENCY_100 25000000UL
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#define ZYNQ_GEM_FREQUENCY_1000 125000000UL
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/* Device registers */
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struct zynq_gem_regs {
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u32 nwctrl; /* 0x0 - Network Control reg */
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u32 nwcfg; /* 0x4 - Network Config reg */
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u32 nwsr; /* 0x8 - Network Status reg */
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u32 reserved1;
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u32 dmacr; /* 0x10 - DMA Control reg */
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u32 txsr; /* 0x14 - TX Status reg */
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u32 rxqbase; /* 0x18 - RX Q Base address reg */
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u32 txqbase; /* 0x1c - TX Q Base address reg */
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u32 rxsr; /* 0x20 - RX Status reg */
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u32 reserved2[2];
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u32 idr; /* 0x2c - Interrupt Disable reg */
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u32 reserved3;
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u32 phymntnc; /* 0x34 - Phy Maintaince reg */
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u32 reserved4[18];
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u32 hashl; /* 0x80 - Hash Low address reg */
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u32 hashh; /* 0x84 - Hash High address reg */
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#define LADDR_LOW 0
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#define LADDR_HIGH 1
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u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
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u32 match[4]; /* 0xa8 - Type ID1 Match reg */
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u32 reserved6[18];
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#define STAT_SIZE 44
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u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
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u32 reserved9[20];
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u32 pcscntrl;
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u32 rserved12[36];
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u32 dcfg6; /* 0x294 Design config reg6 */
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u32 reserved7[106];
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u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
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u32 reserved8[15];
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u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
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u32 reserved10[17];
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u32 upper_txqbase; /* 0x4C8 - Upper tx_q base addr */
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u32 reserved11[2];
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u32 upper_rxqbase; /* 0x4D4 - Upper rx_q base addr */
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};
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/* BD descriptors */
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struct emac_bd {
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u32 addr; /* Next descriptor pointer */
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u32 status;
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#if defined(CONFIG_PHYS_64BIT)
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u32 addr_hi;
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u32 reserved;
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#endif
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};
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#define RX_BUF 32
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/* Page table entries are set to 1MB, or multiples of 1MB
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* (not < 1MB). driver uses less bd's so use 1MB bdspace.
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*/
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#define BD_SPACE 0x100000
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/* BD separation space */
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#define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
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/* Setup the first free TX descriptor */
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#define TX_FREE_DESC 2
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/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
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struct zynq_gem_priv {
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struct emac_bd *tx_bd;
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struct emac_bd *rx_bd;
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char *rxbuffers;
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u32 rxbd_current;
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u32 rx_first_buf;
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int phyaddr;
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int init;
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struct zynq_gem_regs *iobase;
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phy_interface_t interface;
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struct phy_device *phydev;
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ofnode phy_of_node;
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struct mii_dev *bus;
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struct clk clk;
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u32 max_speed;
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bool int_pcs;
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bool dma_64bit;
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};
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static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
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u32 op, u16 *data)
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{
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u32 mgtcr;
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struct zynq_gem_regs *regs = priv->iobase;
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int err;
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err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
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true, 20000, false);
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if (err)
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return err;
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/* Construct mgtcr mask for the operation */
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mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
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(phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
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(regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
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/* Write mgtcr and wait for completion */
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writel(mgtcr, ®s->phymntnc);
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err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
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true, 20000, false);
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if (err)
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return err;
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if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
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*data = readl(®s->phymntnc);
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return 0;
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}
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static int phyread(struct zynq_gem_priv *priv, u32 phy_addr,
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u32 regnum, u16 *val)
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{
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int ret;
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ret = phy_setup_op(priv, phy_addr, regnum,
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ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
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if (!ret)
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debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
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phy_addr, regnum, *val);
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return ret;
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}
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static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
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u32 regnum, u16 data)
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{
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debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
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regnum, data);
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return phy_setup_op(priv, phy_addr, regnum,
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ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
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}
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static int zynq_gem_setup_mac(struct udevice *dev)
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{
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u32 i, macaddrlow, macaddrhigh;
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struct eth_pdata *pdata = dev_get_platdata(dev);
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struct zynq_gem_priv *priv = dev_get_priv(dev);
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struct zynq_gem_regs *regs = priv->iobase;
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/* Set the MAC bits [31:0] in BOT */
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macaddrlow = pdata->enetaddr[0];
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macaddrlow |= pdata->enetaddr[1] << 8;
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macaddrlow |= pdata->enetaddr[2] << 16;
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macaddrlow |= pdata->enetaddr[3] << 24;
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/* Set MAC bits [47:32] in TOP */
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macaddrhigh = pdata->enetaddr[4];
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macaddrhigh |= pdata->enetaddr[5] << 8;
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for (i = 0; i < 4; i++) {
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writel(0, ®s->laddr[i][LADDR_LOW]);
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writel(0, ®s->laddr[i][LADDR_HIGH]);
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/* Do not use MATCHx register */
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writel(0, ®s->match[i]);
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}
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writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
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writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
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return 0;
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}
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static int zynq_phy_init(struct udevice *dev)
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{
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int ret;
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struct zynq_gem_priv *priv = dev_get_priv(dev);
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struct zynq_gem_regs *regs = priv->iobase;
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const u32 supported = SUPPORTED_10baseT_Half |
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SUPPORTED_10baseT_Full |
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SUPPORTED_100baseT_Half |
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SUPPORTED_100baseT_Full |
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SUPPORTED_1000baseT_Half |
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SUPPORTED_1000baseT_Full;
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/* Enable only MDIO bus */
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writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl);
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priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
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priv->interface);
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if (!priv->phydev)
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return -ENODEV;
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if (priv->max_speed) {
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ret = phy_set_supported(priv->phydev, priv->max_speed);
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if (ret)
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return ret;
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}
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priv->phydev->supported &= supported | ADVERTISED_Pause |
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ADVERTISED_Asym_Pause;
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priv->phydev->advertising = priv->phydev->supported;
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priv->phydev->node = priv->phy_of_node;
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return phy_config(priv->phydev);
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}
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static int zynq_gem_init(struct udevice *dev)
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{
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u32 i, nwconfig;
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int ret;
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unsigned long clk_rate = 0;
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struct zynq_gem_priv *priv = dev_get_priv(dev);
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struct zynq_gem_regs *regs = priv->iobase;
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struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
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struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
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if (readl(®s->dcfg6) & ZYNQ_GEM_DCFG_DBG6_DMA_64B)
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priv->dma_64bit = true;
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else
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priv->dma_64bit = false;
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#if defined(CONFIG_PHYS_64BIT)
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if (!priv->dma_64bit) {
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printf("ERR: %s: Using 64-bit DMA but HW doesn't support it\n",
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__func__);
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return -EINVAL;
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}
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#else
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if (priv->dma_64bit)
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debug("WARN: %s: Not using 64-bit dma even HW supports it\n",
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__func__);
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#endif
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if (!priv->init) {
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/* Disable all interrupts */
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writel(0xFFFFFFFF, ®s->idr);
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/* Disable the receiver & transmitter */
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writel(0, ®s->nwctrl);
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writel(0, ®s->txsr);
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writel(0, ®s->rxsr);
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writel(0, ®s->phymntnc);
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/* Clear the Hash registers for the mac address
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* pointed by AddressPtr
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*/
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writel(0x0, ®s->hashl);
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/* Write bits [63:32] in TOP */
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writel(0x0, ®s->hashh);
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/* Clear all counters */
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for (i = 0; i < STAT_SIZE; i++)
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readl(®s->stat[i]);
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/* Setup RxBD space */
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memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
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for (i = 0; i < RX_BUF; i++) {
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priv->rx_bd[i].status = 0xF0000000;
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priv->rx_bd[i].addr =
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(lower_32_bits((ulong)(priv->rxbuffers)
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+ (i * PKTSIZE_ALIGN)));
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#if defined(CONFIG_PHYS_64BIT)
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priv->rx_bd[i].addr_hi =
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(upper_32_bits((ulong)(priv->rxbuffers)
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+ (i * PKTSIZE_ALIGN)));
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#endif
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}
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/* WRAP bit to last BD */
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priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
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/* Write RxBDs to IP */
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writel(lower_32_bits((ulong)priv->rx_bd), ®s->rxqbase);
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#if defined(CONFIG_PHYS_64BIT)
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writel(upper_32_bits((ulong)priv->rx_bd), ®s->upper_rxqbase);
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#endif
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/* Setup for DMA Configuration register */
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writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
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/* Setup for Network Control register, MDIO, Rx and Tx enable */
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setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
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/* Disable the second priority queue */
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dummy_tx_bd->addr = 0;
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#if defined(CONFIG_PHYS_64BIT)
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dummy_tx_bd->addr_hi = 0;
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#endif
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dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
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ZYNQ_GEM_TXBUF_LAST_MASK|
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ZYNQ_GEM_TXBUF_USED_MASK;
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dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
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ZYNQ_GEM_RXBUF_NEW_MASK;
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#if defined(CONFIG_PHYS_64BIT)
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dummy_rx_bd->addr_hi = 0;
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#endif
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dummy_rx_bd->status = 0;
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writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr);
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writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr);
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priv->init++;
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}
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ret = phy_startup(priv->phydev);
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if (ret)
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return ret;
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if (!priv->phydev->link) {
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printf("%s: No link.\n", priv->phydev->dev->name);
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return -1;
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}
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nwconfig = ZYNQ_GEM_NWCFG_INIT;
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/*
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* Set SGMII enable PCS selection only if internal PCS/PMA
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* core is used and interface is SGMII.
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*/
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if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
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priv->int_pcs) {
|
|
nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
|
|
ZYNQ_GEM_NWCFG_PCS_SEL;
|
|
#ifdef CONFIG_ARM64
|
|
writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
|
|
®s->pcscntrl);
|
|
#endif
|
|
}
|
|
|
|
switch (priv->phydev->speed) {
|
|
case SPEED_1000:
|
|
writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
|
|
®s->nwcfg);
|
|
clk_rate = ZYNQ_GEM_FREQUENCY_1000;
|
|
break;
|
|
case SPEED_100:
|
|
writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
|
|
®s->nwcfg);
|
|
clk_rate = ZYNQ_GEM_FREQUENCY_100;
|
|
break;
|
|
case SPEED_10:
|
|
clk_rate = ZYNQ_GEM_FREQUENCY_10;
|
|
break;
|
|
}
|
|
|
|
#if !defined(CONFIG_ARCH_VERSAL)
|
|
ret = clk_set_rate(&priv->clk, clk_rate);
|
|
if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
|
|
dev_err(dev, "failed to set tx clock rate\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_enable(&priv->clk);
|
|
if (ret && ret != -ENOSYS) {
|
|
dev_err(dev, "failed to enable tx clock\n");
|
|
return ret;
|
|
}
|
|
#else
|
|
debug("requested clk_rate %ld\n", clk_rate);
|
|
#endif
|
|
|
|
setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
|
|
ZYNQ_GEM_NWCTRL_TXEN_MASK);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
|
|
{
|
|
dma_addr_t addr;
|
|
u32 size;
|
|
struct zynq_gem_priv *priv = dev_get_priv(dev);
|
|
struct zynq_gem_regs *regs = priv->iobase;
|
|
struct emac_bd *current_bd = &priv->tx_bd[1];
|
|
|
|
/* Setup Tx BD */
|
|
memset(priv->tx_bd, 0, sizeof(struct emac_bd));
|
|
|
|
priv->tx_bd->addr = lower_32_bits((ulong)ptr);
|
|
#if defined(CONFIG_PHYS_64BIT)
|
|
priv->tx_bd->addr_hi = upper_32_bits((ulong)ptr);
|
|
#endif
|
|
priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
|
|
ZYNQ_GEM_TXBUF_LAST_MASK;
|
|
/* Dummy descriptor to mark it as the last in descriptor chain */
|
|
current_bd->addr = 0x0;
|
|
#if defined(CONFIG_PHYS_64BIT)
|
|
current_bd->addr_hi = 0x0;
|
|
#endif
|
|
current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
|
|
ZYNQ_GEM_TXBUF_LAST_MASK|
|
|
ZYNQ_GEM_TXBUF_USED_MASK;
|
|
|
|
/* setup BD */
|
|
writel(lower_32_bits((ulong)priv->tx_bd), ®s->txqbase);
|
|
#if defined(CONFIG_PHYS_64BIT)
|
|
writel(upper_32_bits((ulong)priv->tx_bd), ®s->upper_txqbase);
|
|
#endif
|
|
|
|
addr = (ulong) ptr;
|
|
addr &= ~(ARCH_DMA_MINALIGN - 1);
|
|
size = roundup(len, ARCH_DMA_MINALIGN);
|
|
flush_dcache_range(addr, addr + size);
|
|
barrier();
|
|
|
|
/* Start transmit */
|
|
setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
|
|
|
|
/* Read TX BD status */
|
|
if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
|
|
printf("TX buffers exhausted in mid frame\n");
|
|
|
|
return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE,
|
|
true, 20000, true);
|
|
}
|
|
|
|
/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
|
|
static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
{
|
|
int frame_len;
|
|
dma_addr_t addr;
|
|
struct zynq_gem_priv *priv = dev_get_priv(dev);
|
|
struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
|
|
|
|
if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
|
|
return -1;
|
|
|
|
if (!(current_bd->status &
|
|
(ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
|
|
printf("GEM: SOF or EOF not set for last buffer received!\n");
|
|
return -1;
|
|
}
|
|
|
|
frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
|
|
if (!frame_len) {
|
|
printf("%s: Zero size packet?\n", __func__);
|
|
return -1;
|
|
}
|
|
|
|
#if defined(CONFIG_PHYS_64BIT)
|
|
addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK)
|
|
| ((dma_addr_t)current_bd->addr_hi << 32));
|
|
#else
|
|
addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
|
|
#endif
|
|
addr &= ~(ARCH_DMA_MINALIGN - 1);
|
|
|
|
*packetp = (uchar *)(uintptr_t)addr;
|
|
|
|
invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
|
|
barrier();
|
|
|
|
return frame_len;
|
|
}
|
|
|
|
static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
|
|
{
|
|
struct zynq_gem_priv *priv = dev_get_priv(dev);
|
|
struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
|
|
struct emac_bd *first_bd;
|
|
|
|
if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
|
|
priv->rx_first_buf = priv->rxbd_current;
|
|
} else {
|
|
current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
|
|
current_bd->status = 0xF0000000; /* FIXME */
|
|
}
|
|
|
|
if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
|
|
first_bd = &priv->rx_bd[priv->rx_first_buf];
|
|
first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
|
|
first_bd->status = 0xF0000000;
|
|
}
|
|
|
|
if ((++priv->rxbd_current) >= RX_BUF)
|
|
priv->rxbd_current = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void zynq_gem_halt(struct udevice *dev)
|
|
{
|
|
struct zynq_gem_priv *priv = dev_get_priv(dev);
|
|
struct zynq_gem_regs *regs = priv->iobase;
|
|
|
|
clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
|
|
ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
|
|
}
|
|
|
|
__weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
|
|
{
|
|
return -ENOSYS;
|
|
}
|
|
|
|
static int zynq_gem_read_rom_mac(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
|
|
if (!pdata)
|
|
return -ENOSYS;
|
|
|
|
return zynq_board_read_rom_ethaddr(pdata->enetaddr);
|
|
}
|
|
|
|
static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
|
|
int devad, int reg)
|
|
{
|
|
struct zynq_gem_priv *priv = bus->priv;
|
|
int ret;
|
|
u16 val = 0;
|
|
|
|
ret = phyread(priv, addr, reg, &val);
|
|
debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
|
|
return val;
|
|
}
|
|
|
|
static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
|
|
int reg, u16 value)
|
|
{
|
|
struct zynq_gem_priv *priv = bus->priv;
|
|
|
|
debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
|
|
return phywrite(priv, addr, reg, value);
|
|
}
|
|
|
|
static int zynq_gem_probe(struct udevice *dev)
|
|
{
|
|
void *bd_space;
|
|
struct zynq_gem_priv *priv = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
/* Align rxbuffers to ARCH_DMA_MINALIGN */
|
|
priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
|
|
if (!priv->rxbuffers)
|
|
return -ENOMEM;
|
|
|
|
memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
|
|
u32 addr = (ulong)priv->rxbuffers;
|
|
flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
|
|
barrier();
|
|
|
|
/* Align bd_space to MMU_SECTION_SHIFT */
|
|
bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
|
|
if (!bd_space)
|
|
return -ENOMEM;
|
|
|
|
mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
|
|
BD_SPACE, DCACHE_OFF);
|
|
|
|
/* Initialize the bd spaces for tx and rx bd's */
|
|
priv->tx_bd = (struct emac_bd *)bd_space;
|
|
priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
|
|
|
|
ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to get clock\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
priv->bus = mdio_alloc();
|
|
priv->bus->read = zynq_gem_miiphy_read;
|
|
priv->bus->write = zynq_gem_miiphy_write;
|
|
priv->bus->priv = priv;
|
|
|
|
ret = mdio_register_seq(priv->bus, dev->seq);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return zynq_phy_init(dev);
|
|
}
|
|
|
|
static int zynq_gem_remove(struct udevice *dev)
|
|
{
|
|
struct zynq_gem_priv *priv = dev_get_priv(dev);
|
|
|
|
free(priv->phydev);
|
|
mdio_unregister(priv->bus);
|
|
mdio_free(priv->bus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops zynq_gem_ops = {
|
|
.start = zynq_gem_init,
|
|
.send = zynq_gem_send,
|
|
.recv = zynq_gem_recv,
|
|
.free_pkt = zynq_gem_free_pkt,
|
|
.stop = zynq_gem_halt,
|
|
.write_hwaddr = zynq_gem_setup_mac,
|
|
.read_rom_hwaddr = zynq_gem_read_rom_mac,
|
|
};
|
|
|
|
static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
struct zynq_gem_priv *priv = dev_get_priv(dev);
|
|
struct ofnode_phandle_args phandle_args;
|
|
const char *phy_mode;
|
|
|
|
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
|
|
priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
|
|
/* Hardcode for now */
|
|
priv->phyaddr = -1;
|
|
|
|
if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
|
|
&phandle_args)) {
|
|
debug("phy-handle does exist %s\n", dev->name);
|
|
priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
|
|
"reg", -1);
|
|
priv->phy_of_node = phandle_args.node;
|
|
priv->max_speed = ofnode_read_u32_default(phandle_args.node,
|
|
"max-speed",
|
|
SPEED_1000);
|
|
}
|
|
|
|
phy_mode = dev_read_prop(dev, "phy-mode", NULL);
|
|
if (phy_mode)
|
|
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
|
|
if (pdata->phy_interface == -1) {
|
|
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
|
|
return -EINVAL;
|
|
}
|
|
priv->interface = pdata->phy_interface;
|
|
|
|
priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
|
|
|
|
printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
|
|
priv->phyaddr, phy_string_for_interface(priv->interface));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id zynq_gem_ids[] = {
|
|
{ .compatible = "cdns,zynqmp-gem" },
|
|
{ .compatible = "cdns,zynq-gem" },
|
|
{ .compatible = "cdns,gem" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(zynq_gem) = {
|
|
.name = "zynq_gem",
|
|
.id = UCLASS_ETH,
|
|
.of_match = zynq_gem_ids,
|
|
.ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
|
|
.probe = zynq_gem_probe,
|
|
.remove = zynq_gem_remove,
|
|
.ops = &zynq_gem_ops,
|
|
.priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
|
|
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
|
|
};
|