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https://github.com/brain-hackers/u-boot-brain
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ed32522fe0
Sometimes Read DQ and DQS are not in phase. Since, this phase shift differs from board to board, we need to calibrate it at DRAM init phase, that's read DQ calibration. This patch adds SW Read DQ calibration routine to compensate this skew. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> |
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| .. | ||
| clock_init_exynos4.c | ||
| clock_init_exynos5.c | ||
| clock_init.h | ||
| clock.c | ||
| common_setup.h | ||
| config.mk | ||
| dmc_common.c | ||
| dmc_init_ddr3.c | ||
| dmc_init_exynos4.c | ||
| exynos4_setup.h | ||
| exynos5_setup.h | ||
| lowlevel_init.c | ||
| Makefile | ||
| pinmux.c | ||
| power.c | ||
| soc.c | ||
| spl_boot.c | ||
| system.c | ||
| tzpc.c | ||