mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
25ddd1fb0a
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
354 lines
8.9 KiB
C
354 lines
8.9 KiB
C
/*
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* Voipac PXA270 configuration file
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*
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Board Configuration Options
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*/
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#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
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#define CONFIG_VPAC270 1 /* Voipac PXA270 board */
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#define CONFIG_SYS_TEXT_BASE 0x0
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SYS_MALLOC_LEN (128*1024)
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_BOOTCOMMAND \
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"if mmc init && fatload mmc 0 0xa4000000 uImage; then " \
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"bootm 0xa4000000; " \
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"fi; " \
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"if usb reset && fatload usb 0 0xa4000000 uImage; then " \
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"bootm 0xa4000000; " \
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"fi; " \
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"if ide reset && fatload ide 0 0xa4000000 uImage; then " \
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"bootm 0xa4000000; " \
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"fi; " \
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"bootm 0x60000;"
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#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
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#define CONFIG_TIMESTAMP
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#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_SYS_TEXT_BASE 0x0
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#define CONFIG_LZMA /* LZMA compression support */
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/*
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* Serial Console Configuration
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*/
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#define CONFIG_PXA_SERIAL
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#define CONFIG_FFUART 1
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Bootloader Components Configuration
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_ENV
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#undef CONFIG_CMD_IMLS
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_USB
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#undef CONFIG_LCD
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#define CONFIG_CMD_IDE
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#ifdef CONFIG_ONENAND
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#undef CONFIG_CMD_FLASH
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#define CONFIG_CMD_ONENAND
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#else
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#define CONFIG_CMD_FLASH
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#undef CONFIG_CMD_ONENAND
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#endif
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/*
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* Networking Configuration
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* chip on the Voipac PXA270 board
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*/
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#ifdef CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_NET_MULTI 1
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#define CONFIG_DRIVER_DM9000 1
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#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */
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#define DM9000_IO (CONFIG_DM9000_BASE)
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#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
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#define CONFIG_NET_RETRY_COUNT 10
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#endif
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/*
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* MMC Card Configuration
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*/
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#ifdef CONFIG_CMD_MMC
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#define CONFIG_MMC
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#define CONFIG_PXA_MMC
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#define CONFIG_SYS_MMC_BASE 0xF0000000
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_EXT2
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#define CONFIG_DOS_PARTITION
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#endif
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/*
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* KGDB
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*/
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* HUSH Shell Configuration
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*/
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#define CONFIG_SYS_HUSH_PARSER 1
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_LONGHELP
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT "$ "
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#else
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#define CONFIG_SYS_PROMPT "=> "
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#endif
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_DEVICE_NULLDEV 1
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/*
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* Clock Configuration
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*/
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#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */
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#define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */
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/*
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* Stack sizes
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/*
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* DRAM Map
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*/
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#define CONFIG_NR_DRAM_BANKS 2 /* 2 banks of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
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#ifdef CONFIG_RAM_256M
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#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */
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#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
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#endif
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#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
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#ifdef CONFIG_RAM_256M
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#define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */
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#else
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#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */
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#endif
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#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
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#define CONFIG_SYS_IPL_LOAD_ADDR (0x5c000000)
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_SP_ADDR \
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(PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
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/*
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* NOR FLASH
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*/
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#define CONFIG_SYS_MONITOR_BASE 0x0
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#define CONFIG_SYS_MONITOR_LEN 0x40000
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#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SIZE 0x4000
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#if defined(CONFIG_CMD_FLASH) /* NOR */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#ifdef CONFIG_RAM_256M
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#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */
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#endif
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
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#ifdef CONFIG_RAM_256M
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#define CONFIG_SYS_MAX_FLASH_BANKS 2
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#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
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#else
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#endif
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#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
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#define CONFIG_SYS_FLASH_PROTECTION 1
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#define CONFIG_ENV_IS_IN_FLASH 1
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/*
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* The first four sectors of the NOR flash are 0x8000 bytes big, the rest of the
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* flash consists of 0x20000 bytes big sectors.
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*/
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#if (CONFIG_ENV_ADDR <= 0x18000)
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#define CONFIG_ENV_SECT_SIZE 0x8000
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#else
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#endif
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#elif defined(CONFIG_CMD_ONENAND) /* OneNAND */
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_ONENAND_BASE 0x00000000
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#define CONFIG_ENV_IS_IN_ONENAND 1
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#else /* No flash */
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_ENV_IS_NOWHERE
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#endif
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/*
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* IDE
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*/
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#ifdef CONFIG_CMD_IDE
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#define CONFIG_LBA48
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#undef CONFIG_IDE_LED
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#undef CONFIG_IDE_RESET
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#define __io
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#define CONFIG_SYS_IDE_MAXBUS 1
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#define CONFIG_SYS_IDE_MAXDEVICE 1
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#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
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#define CONFIG_SYS_ATA_DATA_OFFSET 0x120
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#define CONFIG_SYS_ATA_REG_OFFSET 0x120
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x120
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#define CONFIG_SYS_ATA_STRIDE 2
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#endif
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/*
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* GPIO settings
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*/
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#define CONFIG_SYS_GPSR0_VAL 0x01308800
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#define CONFIG_SYS_GPSR1_VAL 0x00cf0000
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#define CONFIG_SYS_GPSR2_VAL 0x922ac000
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#define CONFIG_SYS_GPSR3_VAL 0x0161e800
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#define CONFIG_SYS_GPCR0_VAL 0x00010000
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#define CONFIG_SYS_GPCR1_VAL 0x0
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#define CONFIG_SYS_GPCR2_VAL 0x0
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#define CONFIG_SYS_GPCR3_VAL 0x0
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#define CONFIG_SYS_GPDR0_VAL 0xcbb18800
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#define CONFIG_SYS_GPDR1_VAL 0xfccfa981
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#define CONFIG_SYS_GPDR2_VAL 0x922affff
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#define CONFIG_SYS_GPDR3_VAL 0x0161e904
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#define CONFIG_SYS_GAFR0_L_VAL 0x00100000
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#define CONFIG_SYS_GAFR0_U_VAL 0xa5da8510
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#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
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#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a0aa
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#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
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#define CONFIG_SYS_GAFR2_U_VAL 0x4109a401
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#define CONFIG_SYS_GAFR3_L_VAL 0x54010310
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#define CONFIG_SYS_GAFR3_U_VAL 0x00025401
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#define CONFIG_SYS_PSSR_VAL 0x30
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/*
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* Clock settings
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*/
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#define CONFIG_SYS_CKEN 0x00500240
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#define CONFIG_SYS_CCCR 0x02000290
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/*
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* Memory settings
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*/
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#define CONFIG_SYS_MSC0_VAL 0x3ffc95fa
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#define CONFIG_SYS_MSC1_VAL 0x02ccf974
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#define CONFIG_SYS_MSC2_VAL 0x00000000
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#ifdef CONFIG_RAM_256M
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#define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3
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#else
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#define CONFIG_SYS_MDCNFG_VAL 0x88000ad3
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#endif
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#define CONFIG_SYS_MDREFR_VAL 0x201fe01e
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#define CONFIG_SYS_MDMRS_VAL 0x00000000
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#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
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#define CONFIG_SYS_SXCNFG_VAL 0x40044004
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#define CONFIG_SYS_MEM_BUF_IMP 0x0f
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/*
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* PCMCIA and CF Interfaces
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*/
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#define CONFIG_SYS_MECR_VAL 0x00000001
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#define CONFIG_SYS_MCMEM0_VAL 0x00014307
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#define CONFIG_SYS_MCMEM1_VAL 0x00014307
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#define CONFIG_SYS_MCATT0_VAL 0x0001c787
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#define CONFIG_SYS_MCATT1_VAL 0x0001c787
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#define CONFIG_SYS_MCIO0_VAL 0x0001430f
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#define CONFIG_SYS_MCIO1_VAL 0x0001430f
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/*
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* LCD
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*/
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#ifdef CONFIG_LCD
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#define CONFIG_VOIPAC_LCD
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#endif
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/*
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* USB
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*/
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#ifdef CONFIG_CMD_USB
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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#define CONFIG_SYS_USB_OHCI_BOARD_INIT
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "vpac270"
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#define CONFIG_USB_STORAGE
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#endif
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#endif /* __CONFIG_H */
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