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https://github.com/brain-hackers/u-boot-brain
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25ddd1fb0a
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
216 lines
6.3 KiB
C
216 lines
6.3 KiB
C
/*
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* Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
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*
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* based on previous work by
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*
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* Ulf Samuelsson <ulf@atmel.com>
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* Rick Bronson <rick@efn.org>
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*
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* Configuration settings for the AT91RM9200EK board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __AT91RM9200EK_CONFIG_H__
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#define __AT91RM9200EK_CONFIG_H__
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#include <asm/sizes.h>
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/*
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* AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
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* AT91C_MAIN_CLOCK is the frequency of PLLA output
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* AT91C_MASTER_CLOCK is the peripherial clock
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* CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
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* set in arch/arm/cpu/arm920t/at91/timer.c)
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* CONFIG_SYS_HZ is the tick rate for timer tc0
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*/
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#define AT91C_XTAL_CLOCK 18432000
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#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
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#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 )
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#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
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#define CONFIG_SYS_HZ 1000
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/* CPU configuration */
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#define CONFIG_ARM920T
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#define CONFIG_AT91RM9200
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#define CONFIG_AT91RM9200EK
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#define CONFIG_CPUAT91
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#define USE_920T_MMU
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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/*
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* Memory Configuration
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE SZ_32M
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END \
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(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
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/*
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* LowLevel Init
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_USE_MAIN_OSCILLATOR
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/* flash */
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#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
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#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
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/* clocks */
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#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
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#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
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/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
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#define CONFIG_SYS_MCKR_VAL 0x00000202
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/* sdram */
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#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
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#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
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#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
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#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
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#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
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#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
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#define CONFIG_SYS_SDRAM1 CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
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#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
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#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
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#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
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#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
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#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
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#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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/*
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* Hardware drivers
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*/
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/*
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* Choose a USART for serial console
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* CONFIG_DBGU is DBGU unit on J10
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* CONFIG_USART1 is USART1 on J14
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*/
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#define CONFIG_AT91RM9200_USART
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#define CONFIG_DBGU
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#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
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#define CONFIG_BAUDRATE 115200
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_USB
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#undef CONFIG_CMD_FPGA
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/*
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* Network Driver Setting
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*/
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#define CONFIG_NET_MULTI
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#define CONFIG_DRIVER_AT91EMAC
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#define CONFIG_SYS_RX_ETH_BUFFER 16
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#define CONFIG_RMII
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#define CONFIG_MII
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/*
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* NOR Flash
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*/
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_BASE 0x10000000
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#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
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#define PHYS_FLASH_SIZE SZ_8M
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_FLASH_PROTECTION
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/*
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* USB Config
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*/
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#define CONFIG_USB_ATMEL 1
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#define CONFIG_USB_OHCI_NEW 1
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#define CONFIG_USB_KEYBOARD 1
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#define CONFIG_USB_STORAGE 1
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#define CONFIG_DOS_PARTITION 1
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#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
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#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
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/*
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* Environment Settings
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*/
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#define CONFIG_ENV_IS_IN_FLASH
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/*
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* after u-boot.bin
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*/
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#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SIZE SZ_64K /* sectors are 64K here */
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/* The following #defines are needed to get flash environment right */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MONITOR_LEN SZ_256K
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/*
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* Boot option
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*/
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#define CONFIG_BOOTDELAY 3
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/* default load address */
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#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M
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#define CONFIG_ENV_OVERWRITE
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/*
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* Shell Settings
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*/
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT "U-Boot> "
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
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SZ_4K)
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/* size in bytes reserved for initial data */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
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- GENERATED_GBL_DATA_SIZE)
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#define CONFIG_STACKSIZE SZ_32K /* regular stack */
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#define CONFIG_STACKSIZE_IRQ SZ_4K /* Unsure if to big or to small*/
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#define CONFIG_STACKSIZE_FIQ SZ_4K /* Unsure if to big or to small*/
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#endif /* __AT91RM9200EK_CONFIG_H__ */
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