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https://github.com/brain-hackers/u-boot-brain
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The NAND flash on the TQM8548_BE modules requires a short delay after running the UPM pattern like the MPC8360ERDK board does. The TQM8548_BE requires a further short delay after writing out a buffer. Normally the R/B pin should be checked, but it's not connected on the TQM8548_BE. The corresponding Linux FSL UPM driver uses similar delay points at the same locations. To manage these extra delays in a more general way, I introduced the "wait_flags" field allowing the board-specific driver to specify various types of extra delay. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
49 lines
1.0 KiB
C
49 lines
1.0 KiB
C
/*
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* FSL UPM NAND driver
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __LINUX_MTD_NAND_FSL_UPM
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#define __LINUX_MTD_NAND_FSL_UPM
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#include <linux/mtd/nand.h>
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#define FSL_UPM_WAIT_RUN_PATTERN 0x1
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#define FSL_UPM_WAIT_WRITE_BYTE 0x2
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#define FSL_UPM_WAIT_WRITE_BUFFER 0x4
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struct fsl_upm {
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void __iomem *mdr;
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void __iomem *mxmr;
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void __iomem *mar;
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void __iomem *io_addr;
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};
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struct fsl_upm_nand {
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struct fsl_upm upm;
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int width;
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int upm_cmd_offset;
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int upm_addr_offset;
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int upm_mar_chip_offset;
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int wait_flags;
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int (*dev_ready)(int chip_nr);
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int chip_delay;
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int chip_offset;
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int chip_nr;
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/* no need to fill */
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int last_ctrl;
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};
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extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun);
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#endif
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