mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 20:56:16 +09:00
10cbe3b6a4
These are all the files which use the API incorrectly but did not get built using MAKEALL -a powerpc|arm. I have no compiler for them, but the remaining issues should be far less than without this patch. Any outstanding issues are left to the maintainers of boards that use these drivers. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
587 lines
14 KiB
C
587 lines
14 KiB
C
/*
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* (C) Copyright 2010
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Designware ethernet IP driver for u-boot
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <malloc.h>
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#include <linux/err.h>
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#include <asm/io.h>
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#include "designware.h"
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static int configure_phy(struct eth_device *dev);
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static void tx_descs_init(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
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char *txbuffs = &priv->txbuffs[0];
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struct dmamacdescr *desc_p;
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u32 idx;
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for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
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desc_p = &desc_table_p[idx];
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desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
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desc_p->dmamac_next = &desc_table_p[idx + 1];
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
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DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
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DESC_TXSTS_TXCHECKINSCTRL | \
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DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
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desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
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desc_p->dmamac_cntl = 0;
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desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
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#else
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desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
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desc_p->txrx_status = 0;
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#endif
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}
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/* Correcting the last pointer of the chain */
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desc_p->dmamac_next = &desc_table_p[0];
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writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
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}
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static void rx_descs_init(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
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char *rxbuffs = &priv->rxbuffs[0];
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struct dmamacdescr *desc_p;
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u32 idx;
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for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
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desc_p = &desc_table_p[idx];
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desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
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desc_p->dmamac_next = &desc_table_p[idx + 1];
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desc_p->dmamac_cntl =
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(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
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DESC_RXCTRL_RXCHAIN;
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desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
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}
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/* Correcting the last pointer of the chain */
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desc_p->dmamac_next = &desc_table_p[0];
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writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
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}
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static void descs_init(struct eth_device *dev)
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{
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tx_descs_init(dev);
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rx_descs_init(dev);
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}
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static int mac_reset(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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ulong start;
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int timeout = CONFIG_MACRESET_TIMEOUT;
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writel(DMAMAC_SRST, &dma_p->busmode);
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writel(MII_PORTSELECT, &mac_p->conf);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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if (!(readl(&dma_p->busmode) & DMAMAC_SRST))
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return 0;
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/* Try again after 10usec */
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udelay(10);
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};
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return -1;
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}
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static int dw_write_hwaddr(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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u32 macid_lo, macid_hi;
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u8 *mac_id = &dev->enetaddr[0];
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macid_lo = mac_id[0] + (mac_id[1] << 8) + \
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(mac_id[2] << 16) + (mac_id[3] << 24);
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macid_hi = mac_id[4] + (mac_id[5] << 8);
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writel(macid_hi, &mac_p->macaddr0hi);
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writel(macid_lo, &mac_p->macaddr0lo);
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return 0;
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}
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static int dw_eth_init(struct eth_device *dev, bd_t *bis)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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u32 conf;
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if (priv->phy_configured != 1)
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configure_phy(dev);
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/* Reset ethernet hardware */
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if (mac_reset(dev) < 0)
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return -1;
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/* Resore the HW MAC address as it has been lost during MAC reset */
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dw_write_hwaddr(dev);
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writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
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&dma_p->busmode);
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writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode);
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writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode);
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conf = FRAMEBURSTENABLE | DISABLERXOWN;
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if (priv->speed != SPEED_1000M)
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conf |= MII_PORTSELECT;
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if (priv->duplex == FULL_DUPLEX)
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conf |= FULLDPLXMODE;
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writel(conf, &mac_p->conf);
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descs_init(dev);
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/*
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* Start/Enable xfer at dma as well as mac level
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*/
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writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
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writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
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writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
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return 0;
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}
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static int dw_eth_send(struct eth_device *dev, void *packet, int length)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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u32 desc_num = priv->tx_currdescnum;
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struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
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/* Check if the descriptor is owned by CPU */
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if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
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printf("CPU not owner of tx frame\n");
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return -1;
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}
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memcpy((void *)desc_p->dmamac_addr, packet, length);
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
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desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
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DESC_TXCTRL_SIZE1MASK;
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desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
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desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
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#else
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desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
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DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
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DESC_TXCTRL_TXFIRST;
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desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
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#endif
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/* Test the wrap-around condition. */
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if (++desc_num >= CONFIG_TX_DESCR_NUM)
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desc_num = 0;
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priv->tx_currdescnum = desc_num;
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/* Start the transmission */
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writel(POLL_DATA, &dma_p->txpolldemand);
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return 0;
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}
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static int dw_eth_recv(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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u32 desc_num = priv->rx_currdescnum;
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struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
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u32 status = desc_p->txrx_status;
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int length = 0;
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/* Check if the owner is the CPU */
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if (!(status & DESC_RXSTS_OWNBYDMA)) {
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length = (status & DESC_RXSTS_FRMLENMSK) >> \
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DESC_RXSTS_FRMLENSHFT;
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NetReceive(desc_p->dmamac_addr, length);
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/*
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* Make the current descriptor valid again and go to
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* the next one
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*/
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desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
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/* Test the wrap-around condition. */
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if (++desc_num >= CONFIG_RX_DESCR_NUM)
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desc_num = 0;
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}
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priv->rx_currdescnum = desc_num;
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return length;
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}
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static void dw_eth_halt(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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mac_reset(dev);
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priv->tx_currdescnum = priv->rx_currdescnum = 0;
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}
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static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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ulong start;
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u32 miiaddr;
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int timeout = CONFIG_MDIO_TIMEOUT;
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miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
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((reg << MIIREGSHIFT) & MII_REGMSK);
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writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
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*val = readl(&mac_p->miidata);
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return 0;
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}
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/* Try again after 10usec */
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udelay(10);
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};
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return -1;
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}
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static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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ulong start;
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u32 miiaddr;
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int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
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u16 value;
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writel(val, &mac_p->miidata);
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miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
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((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
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writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
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ret = 0;
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break;
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}
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/* Try again after 10usec */
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udelay(10);
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};
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/* Needed as a fix for ST-Phy */
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eth_mdio_read(dev, addr, reg, &value);
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return ret;
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}
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#if defined(CONFIG_DW_SEARCH_PHY)
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static int find_phy(struct eth_device *dev)
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{
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int phy_addr = 0;
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u16 ctrl, oldctrl;
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do {
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eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
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oldctrl = ctrl & BMCR_ANENABLE;
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ctrl ^= BMCR_ANENABLE;
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eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
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eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
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ctrl &= BMCR_ANENABLE;
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if (ctrl == oldctrl) {
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phy_addr++;
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} else {
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ctrl ^= BMCR_ANENABLE;
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eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
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return phy_addr;
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}
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} while (phy_addr < 32);
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return -1;
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}
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#endif
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static int dw_reset_phy(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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u16 ctrl;
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ulong start;
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int timeout = CONFIG_PHYRESET_TIMEOUT;
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u32 phy_addr = priv->address;
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eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
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if (!(ctrl & BMCR_RESET))
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break;
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/* Try again after 10usec */
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udelay(10);
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};
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if (get_timer(start) >= CONFIG_PHYRESET_TIMEOUT)
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return -1;
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#ifdef CONFIG_PHY_RESET_DELAY
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udelay(CONFIG_PHY_RESET_DELAY);
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#endif
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return 0;
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}
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static int configure_phy(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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int phy_addr;
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u16 bmcr;
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#if defined(CONFIG_DW_AUTONEG)
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u16 bmsr;
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u32 timeout;
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ulong start;
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u16 anlpar, btsr;
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#else
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u16 ctrl;
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#endif
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#if defined(CONFIG_DW_SEARCH_PHY)
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phy_addr = find_phy(dev);
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if (phy_addr >= 0)
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priv->address = phy_addr;
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else
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return -1;
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#else
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phy_addr = priv->address;
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#endif
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if (dw_reset_phy(dev) < 0)
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return -1;
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#if defined(CONFIG_DW_AUTONEG)
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/* Set Auto-Neg Advertisement capabilities to 10/100 half/full */
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eth_mdio_write(dev, phy_addr, MII_ADVERTISE, 0x1E1);
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bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
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#else
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bmcr = BMCR_SPEED100 | BMCR_FULLDPLX;
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#if defined(CONFIG_DW_SPEED10M)
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bmcr &= ~BMCR_SPEED100;
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#endif
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#if defined(CONFIG_DW_DUPLEXHALF)
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bmcr &= ~BMCR_FULLDPLX;
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#endif
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#endif
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if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
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return -1;
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/* Read the phy status register and populate priv structure */
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#if defined(CONFIG_DW_AUTONEG)
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timeout = CONFIG_AUTONEG_TIMEOUT;
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr);
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if (bmsr & BMSR_ANEGCOMPLETE)
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break;
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/* Try again after 10usec */
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udelay(10);
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};
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eth_mdio_read(dev, phy_addr, MII_LPA, &anlpar);
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eth_mdio_read(dev, phy_addr, MII_STAT1000, &btsr);
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if (bmsr & BMSR_ANEGCOMPLETE) {
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if (btsr & PHY_1000BTSR_1000FD) {
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priv->speed = SPEED_1000M;
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bmcr |= BMCR_SPEED1000;
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priv->duplex = FULL_DUPLEX;
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bmcr |= BMCR_FULLDPLX;
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} else if (btsr & PHY_1000BTSR_1000HD) {
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priv->speed = SPEED_1000M;
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bmcr |= BMCR_SPEED1000;
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priv->duplex = HALF_DUPLEX;
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bmcr &= ~BMCR_FULLDPLX;
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} else if (anlpar & LPA_100FULL) {
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priv->speed = SPEED_100M;
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bmcr |= BMCR_SPEED100;
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priv->duplex = FULL_DUPLEX;
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bmcr |= BMCR_FULLDPLX;
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} else if (anlpar & LPA_100HALF) {
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priv->speed = SPEED_100M;
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bmcr |= BMCR_SPEED100;
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priv->duplex = HALF_DUPLEX;
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bmcr &= ~BMCR_FULLDPLX;
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} else if (anlpar & LPA_10FULL) {
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priv->speed = SPEED_10M;
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bmcr &= ~BMCR_SPEED100;
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priv->duplex = FULL_DUPLEX;
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bmcr |= BMCR_FULLDPLX;
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} else {
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priv->speed = SPEED_10M;
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bmcr &= ~BMCR_SPEED100;
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priv->duplex = HALF_DUPLEX;
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bmcr &= ~BMCR_FULLDPLX;
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}
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if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
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return -1;
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} else
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return -1;
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#else
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|
if (eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl) < 0)
|
|
return -1;
|
|
|
|
if (ctrl & BMCR_FULLDPLX)
|
|
priv->duplex = FULL_DUPLEX;
|
|
else
|
|
priv->duplex = HALF_DUPLEX;
|
|
|
|
if (ctrl & BMCR_SPEED1000)
|
|
priv->speed = SPEED_1000M;
|
|
else if (ctrl & BMCR_SPEED100)
|
|
priv->speed = SPEED_100M;
|
|
else
|
|
priv->speed = SPEED_10M;
|
|
#endif
|
|
priv->phy_configured = 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_MII)
|
|
static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val)
|
|
{
|
|
struct eth_device *dev;
|
|
|
|
dev = eth_get_dev_by_name(devname);
|
|
if (dev)
|
|
eth_mdio_read(dev, addr, reg, val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val)
|
|
{
|
|
struct eth_device *dev;
|
|
|
|
dev = eth_get_dev_by_name(devname);
|
|
if (dev)
|
|
eth_mdio_write(dev, addr, reg, val);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int designware_initialize(u32 id, ulong base_addr, u32 phy_addr)
|
|
{
|
|
struct eth_device *dev;
|
|
struct dw_eth_dev *priv;
|
|
|
|
dev = (struct eth_device *) malloc(sizeof(struct eth_device));
|
|
if (!dev)
|
|
return -ENOMEM;
|
|
|
|
/*
|
|
* Since the priv structure contains the descriptors which need a strict
|
|
* buswidth alignment, memalign is used to allocate memory
|
|
*/
|
|
priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev));
|
|
if (!priv) {
|
|
free(dev);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
memset(dev, 0, sizeof(struct eth_device));
|
|
memset(priv, 0, sizeof(struct dw_eth_dev));
|
|
|
|
sprintf(dev->name, "mii%d", id);
|
|
dev->iobase = (int)base_addr;
|
|
dev->priv = priv;
|
|
|
|
eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]);
|
|
|
|
priv->dev = dev;
|
|
priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
|
|
priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
|
|
DW_DMA_BASE_OFFSET);
|
|
priv->address = phy_addr;
|
|
priv->phy_configured = 0;
|
|
|
|
if (mac_reset(dev) < 0)
|
|
return -1;
|
|
|
|
configure_phy(dev);
|
|
|
|
dev->init = dw_eth_init;
|
|
dev->send = dw_eth_send;
|
|
dev->recv = dw_eth_recv;
|
|
dev->halt = dw_eth_halt;
|
|
dev->write_hwaddr = dw_write_hwaddr;
|
|
|
|
eth_register(dev);
|
|
|
|
#if defined(CONFIG_MII)
|
|
miiphy_register(dev->name, dw_mii_read, dw_mii_write);
|
|
#endif
|
|
return 1;
|
|
}
|