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https://github.com/brain-hackers/u-boot-brain
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4f2532c4a4
Enable sync of DDR refresh for LS2085a platform. GPP DDR controllers stay in sync. DP-DDR has only one controller so it does no harm. Signed-off-by: York Sun <yorksun@freescale.com>
25 lines
601 B
C
25 lines
601 B
C
/*
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* Copyright 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __LS2_EMU_H
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#define __LS2_EMU_H
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#include "ls2085a_common.h"
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#define CONFIG_IDENT_STRING " LS2085A-EMU"
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#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU"
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#define CONFIG_DDR_SPD
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#define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */
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#define SPD_EEPROM_ADDRESS1 0x51
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#define SPD_EEPROM_ADDRESS2 0x52
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#define SPD_EEPROM_ADDRESS3 0x53
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#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
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#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */
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#define CONFIG_FSL_DDR_SYNC_REFRESH
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#endif /* __LS2_EMU_H */
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