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![Wolfgang Denk](/assets/img/avatar_default.png)
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
221 lines
4.8 KiB
C
221 lines
4.8 KiB
C
/*
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* (C) Copyright 2003
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* MuLogic B.V.
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*
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* (C) Copyright 2002
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* Simple Network Magic Corporation, dnevil@snmc.com
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/u-boot.h>
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#include <commproc.h>
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#include "mpc8xx.h"
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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/* ------------------------------------------------------------------------- */
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const uint sdram_table[] =
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{
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
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0x1FF77C47, 0x1FF77C35, 0xEFEABC34, 0x1FB57C35,
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/*
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* Burst Read. (Offset 8 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
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0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47,
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0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
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0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47,
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0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
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/*
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* Burst Write. (Offset 20 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
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0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, 0xFFFFEC04,
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0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
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0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
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/*
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* Refresh (Offset 30 in UPMA RAM)
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*/
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0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC84, 0xFFFFFC07, 0xFFFFEC04, 0xFFFFEC04,
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0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
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/*
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* Exception. (Offset 3c in UPMA RAM)
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*/
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0x7FFFFC07, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*
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* Test ID string (QS860T...)
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*
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* Always return 1
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*/
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int checkboard (void)
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{
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char *s, *e;
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char buf[64];
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int i;
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i = getenv_f("serial#", buf, sizeof(buf));
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s = (i>0) ? buf : NULL;
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if (!s || strncmp(s, "QS860T", 6)) {
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puts ("### No HW ID - assuming QS860T");
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} else {
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for (e=s; *e; ++e) {
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if (*e == ' ')
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break;
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}
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for ( ; s<e; ++s) {
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putc (*s);
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}
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}
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putc ('\n');
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size;
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upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
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/*
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* Prescaler for refresh
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*/
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memctl->memc_mptpr = 0x0400;
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/*
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* Map controller bank 2 to the SDRAM address
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*/
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memctl->memc_or2 = CONFIG_SYS_OR2;
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memctl->memc_br2 = CONFIG_SYS_BR2;
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udelay(200);
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/* perform SDRAM initialization sequence */
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memctl->memc_mbmr = CONFIG_SYS_16M_MBMR;
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udelay(100);
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memctl->memc_mar = 0x00000088;
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memctl->memc_mcr = 0x80804105; /* run precharge pattern */
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udelay(1);
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/* Run two refresh cycles on SDRAM */
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memctl->memc_mbmr = 0x18802118;
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memctl->memc_mcr = 0x80804130;
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memctl->memc_mbmr = 0x18802114;
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memctl->memc_mcr = 0x80804106;
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udelay (1000);
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#if 0
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/*
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* Check for 64M SDRAM Memory Size
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*/
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size = dram_size (CONFIG_SYS_64M_MBMR, (ulong *)SDRAM_BASE, SDRAM_64M_MAX_SIZE);
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udelay (1000);
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/*
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* Check for 16M SDRAM Memory Size
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*/
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if (size != SDRAM_64M_MAX_SIZE) {
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#endif
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size = dram_size (CONFIG_SYS_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
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udelay (1000);
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#if 0
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}
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memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
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#endif
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udelay(10000);
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#if 0
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/*
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* Also, map other memory to correct position
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*/
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/*
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* Map the 8M Intel Flash device to chip select 1
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*/
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memctl->memc_or1 = CONFIG_SYS_OR1;
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memctl->memc_br1 = CONFIG_SYS_BR1;
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/*
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* Map 64K NVRAM, Sipex Device, NAND Ctl Reg, and LED Ctl Reg
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* to chip select 3
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*/
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memctl->memc_or3 = CONFIG_SYS_OR3;
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memctl->memc_br3 = CONFIG_SYS_BR3;
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/*
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* Map chip selects 4, 5, 6, & 7 for external expansion connector
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*/
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memctl->memc_or4 = CONFIG_SYS_OR4;
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memctl->memc_br4 = CONFIG_SYS_BR4;
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memctl->memc_or5 = CONFIG_SYS_OR5;
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memctl->memc_br5 = CONFIG_SYS_BR5;
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memctl->memc_or6 = CONFIG_SYS_OR6;
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memctl->memc_br6 = CONFIG_SYS_BR6;
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memctl->memc_or7 = CONFIG_SYS_OR7;
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memctl->memc_br7 = CONFIG_SYS_BR7;
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#endif
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return (size);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mbmr_value, long int *base, long int maxsize)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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memctl->memc_mbmr = mbmr_value;
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return (get_ram_size(base, maxsize));
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}
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